v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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constant-riscv-a.h
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1// Copyright 2022 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_CODEGEN_RISCV_CONSTANT_RISCV_A_H_
6#define V8_CODEGEN_RISCV_CONSTANT_RISCV_A_H_
7
9namespace v8 {
10namespace internal {
11
12// RV32A Standard Extension
13constexpr Opcode RO_LR_W =
14 AMO | (0b010 << kFunct3Shift) | (0b00010 << kFunct5Shift);
15constexpr Opcode RO_SC_W =
16 AMO | (0b010 << kFunct3Shift) | (0b00011 << kFunct5Shift);
18 AMO | (0b010 << kFunct3Shift) | (0b00001 << kFunct5Shift);
20 AMO | (0b010 << kFunct3Shift) | (0b00000 << kFunct5Shift);
22 AMO | (0b010 << kFunct3Shift) | (0b00100 << kFunct5Shift);
24 AMO | (0b010 << kFunct3Shift) | (0b01100 << kFunct5Shift);
25constexpr Opcode RO_AMOOR_W =
26 AMO | (0b010 << kFunct3Shift) | (0b01000 << kFunct5Shift);
28 AMO | (0b010 << kFunct3Shift) | (0b10000 << kFunct5Shift);
30 AMO | (0b010 << kFunct3Shift) | (0b10100 << kFunct5Shift);
32 AMO | (0b010 << kFunct3Shift) | (0b11000 << kFunct5Shift);
34 AMO | (0b010 << kFunct3Shift) | (0b11100 << kFunct5Shift);
35
36#ifdef V8_TARGET_ARCH_RISCV64
37 // RV64A Standard Extension (in addition to RV32A)
38constexpr Opcode RO_LR_D =
39 AMO | (0b011 << kFunct3Shift) | (0b00010 << kFunct5Shift);
40constexpr Opcode RO_SC_D =
41 AMO | (0b011 << kFunct3Shift) | (0b00011 << kFunct5Shift);
42constexpr Opcode RO_AMOSWAP_D =
43 AMO | (0b011 << kFunct3Shift) | (0b00001 << kFunct5Shift);
44constexpr Opcode RO_AMOADD_D =
45 AMO | (0b011 << kFunct3Shift) | (0b00000 << kFunct5Shift);
46constexpr Opcode RO_AMOXOR_D =
47 AMO | (0b011 << kFunct3Shift) | (0b00100 << kFunct5Shift);
48constexpr Opcode RO_AMOAND_D =
49 AMO | (0b011 << kFunct3Shift) | (0b01100 << kFunct5Shift);
50constexpr Opcode RO_AMOOR_D =
51 AMO | (0b011 << kFunct3Shift) | (0b01000 << kFunct5Shift);
52constexpr Opcode RO_AMOMIN_D =
53 AMO | (0b011 << kFunct3Shift) | (0b10000 << kFunct5Shift);
54constexpr Opcode RO_AMOMAX_D =
55 AMO | (0b011 << kFunct3Shift) | (0b10100 << kFunct5Shift);
56constexpr Opcode RO_AMOMINU_D =
57 AMO | (0b011 << kFunct3Shift) | (0b11000 << kFunct5Shift);
58constexpr Opcode RO_AMOMAXU_D =
59 AMO | (0b011 << kFunct3Shift) | (0b11100 << kFunct5Shift);
60#endif // V8_TARGET_ARCH_RISCV64
61// clang-format on
62} // namespace internal
63} // namespace v8
64
65#endif // V8_CODEGEN_RISCV_CONSTANT_RISCV_A_H_
constexpr Opcode RO_SC_W
constexpr Opcode RO_AMOMAX_W
constexpr Opcode RO_AMOOR_W
constexpr Opcode RO_AMOADD_W
constexpr Opcode RO_AMOMINU_W
constexpr Opcode RO_AMOMAXU_W
constexpr Opcode RO_AMOAND_W
constexpr Opcode RO_AMOMIN_W
constexpr Opcode RO_AMOSWAP_W
constexpr Opcode RO_LR_W
constexpr Opcode RO_AMOXOR_W