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instruction-codes-arm64.h
Go to the documentation of this file.
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// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef V8_COMPILER_BACKEND_ARM64_INSTRUCTION_CODES_ARM64_H_
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#define V8_COMPILER_BACKEND_ARM64_INSTRUCTION_CODES_ARM64_H_
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namespace
v8
{
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namespace
internal
{
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namespace
compiler {
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// ARM64-specific opcodes that specify which assembly sequence to emit.
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// Most opcodes specify a single instruction.
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// Opcodes that support a MemoryAccessMode.
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#define TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \
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V(Arm64Ldr) \
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V(Arm64Ldrb) \
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V(Arm64LdrD) \
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V(Arm64Ldrh) \
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V(Arm64LdrQ) \
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V(Arm64LdrS) \
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V(Arm64LdrH) \
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V(Arm64Ldrsb) \
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V(Arm64LdrsbW) \
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V(Arm64Ldrsh) \
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V(Arm64LdrshW) \
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V(Arm64Ldrsw) \
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V(Arm64LdrW) \
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IF_WASM(V, Arm64LoadLane) \
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IF_WASM(V, Arm64LoadSplat) \
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IF_WASM(V, Arm64S128Load16x4S) \
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IF_WASM(V, Arm64S128Load16x4U) \
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IF_WASM(V, Arm64S128Load32x2S) \
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IF_WASM(V, Arm64S128Load32x2U) \
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IF_WASM(V, Arm64S128Load8x8S) \
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IF_WASM(V, Arm64S128Load8x8U) \
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IF_WASM(V, Arm64StoreLane) \
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IF_WASM(V, Arm64S128LoadPairDeinterleave) \
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V(Arm64Str) \
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V(Arm64StrPair) \
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V(Arm64Strb) \
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V(Arm64StrD) \
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V(Arm64Strh) \
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V(Arm64StrQ) \
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V(Arm64StrS) \
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V(Arm64StrH) \
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V(Arm64StrW) \
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V(Arm64StrWPair) \
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V(Arm64LdrDecompressTaggedSigned) \
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V(Arm64LdrDecompressTagged) \
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V(Arm64LdrDecompressProtected) \
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V(Arm64StrCompressTagged) \
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V(Arm64Word64AtomicLoadUint64) \
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V(Arm64Word64AtomicStoreWord64)
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#define TARGET_ARCH_SIMD_OPCODE_LIST(V) \
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V(Arm64F64x2Qfma) \
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V(Arm64F64x2Qfms) \
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V(Arm64F64x2Pmin) \
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V(Arm64F64x2Pmax) \
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V(Arm64F64x2ConvertLowI32x4S) \
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V(Arm64F64x2ConvertLowI32x4U) \
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V(Arm64F64x2PromoteLowF32x4) \
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V(Arm64F32x4SConvertI32x4) \
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V(Arm64F32x4UConvertI32x4) \
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V(Arm64F32x4Qfma) \
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V(Arm64F32x4Qfms) \
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V(Arm64F32x4Pmin) \
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V(Arm64F32x4Pmax) \
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V(Arm64F32x4DemoteF64x2Zero) \
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V(Arm64F16x8Pmin) \
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V(Arm64F16x8Pmax) \
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V(Arm64F32x4PromoteLowF16x8) \
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V(Arm64F16x8SConvertI16x8) \
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V(Arm64F16x8UConvertI16x8) \
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V(Arm64F16x8DemoteF32x4Zero) \
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V(Arm64F16x8DemoteF64x2Zero) \
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V(Arm64I16x8SConvertF16x8) \
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V(Arm64I16x8UConvertF16x8) \
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V(Arm64F16x8Qfma) \
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V(Arm64F16x8Qfms) \
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V(Arm64I64x2ShrU) \
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V(Arm64I64x2BitMask) \
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V(Arm64I32x4SConvertF32x4) \
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V(Arm64I32x4Shl) \
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V(Arm64I32x4ShrS) \
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V(Arm64I32x4Mul) \
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V(Arm64I16x8Q15MulRSatS) \
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V(Arm64I16x8BitMask) \
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V(Arm64I8x16Shl) \
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V(Arm64I8x16ShrS) \
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V(Arm64I8x16SConvertI16x8) \
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V(Arm64I8x16ShrU) \
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V(Arm64I8x16UConvertI16x8) \
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V(Arm64I8x16BitMask) \
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V(Arm64S128Const) \
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V(Arm64S128Dup) \
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V(Arm64S128And) \
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V(Arm64S128Or) \
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V(Arm64S128Xor) \
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V(Arm64S128Not) \
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V(Arm64S128Select) \
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V(Arm64S128AndNot) \
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V(Arm64Ssra) \
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V(Arm64Usra) \
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V(Arm64S64x2UnzipLeft) \
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V(Arm64S64x2UnzipRight) \
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V(Arm64S32x4ZipLeft) \
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V(Arm64S32x4ZipRight) \
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V(Arm64S32x4UnzipLeft) \
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V(Arm64S32x4UnzipRight) \
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V(Arm64S32x4TransposeLeft) \
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V(Arm64S32x4TransposeRight) \
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V(Arm64S64x2Shuffle) \
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V(Arm64S64x1Shuffle) \
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V(Arm64S32x4Shuffle) \
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V(Arm64S32x2Shuffle) \
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V(Arm64S32x1Shuffle) \
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V(Arm64S16x2Shuffle) \
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V(Arm64S16x1Shuffle) \
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V(Arm64S8x2Shuffle) \
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V(Arm64S16x8ZipLeft) \
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V(Arm64S16x8ZipRight) \
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V(Arm64S16x8UnzipLeft) \
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V(Arm64S16x8UnzipRight) \
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V(Arm64S16x8TransposeLeft) \
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V(Arm64S16x8TransposeRight) \
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V(Arm64S8x16ZipLeft) \
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V(Arm64S8x16ZipRight) \
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V(Arm64S8x16UnzipLeft) \
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V(Arm64S8x16UnzipRight) \
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V(Arm64S8x16TransposeLeft) \
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V(Arm64S8x16TransposeRight) \
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V(Arm64S8x16Concat) \
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V(Arm64I8x16Swizzle) \
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V(Arm64I8x16Shuffle) \
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V(Arm64S32x4Reverse) \
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V(Arm64S32x4OneLaneSwizzle) \
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V(Arm64S32x2Reverse) \
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V(Arm64S16x4Reverse) \
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V(Arm64S16x2Reverse) \
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V(Arm64S8x8Reverse) \
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V(Arm64S8x4Reverse) \
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V(Arm64S8x2Reverse) \
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V(Arm64V128AnyTrue) \
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V(Arm64I64x2AllTrue) \
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V(Arm64I32x4AllTrue) \
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V(Arm64I16x8AllTrue) \
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V(Arm64I8x16AllTrue) \
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V(Arm64Sxtl) \
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V(Arm64Sxtl2) \
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V(Arm64Uxtl) \
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V(Arm64Uxtl2) \
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V(Arm64FSplat) \
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V(Arm64FAbs) \
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V(Arm64FSqrt) \
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V(Arm64FNeg) \
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V(Arm64FExtractLane) \
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V(Arm64FReplaceLane) \
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V(Arm64ISplat) \
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V(Arm64IAbs) \
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V(Arm64INeg) \
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V(Arm64IExtractLane) \
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V(Arm64IReplaceLane) \
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V(Arm64I64x2Shl) \
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V(Arm64I64x2ShrS) \
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V(Arm64I64x2Mul) \
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V(Arm64I32x4UConvertF32x4) \
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V(Arm64I32x4ShrU) \
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V(Arm64I32x4BitMask) \
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V(Arm64I32x4DotI16x8S) \
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V(Arm64I16x8DotI8x16S) \
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V(Arm64I32x4DotI8x16AddS) \
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V(Arm64I8x16Addv) \
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V(Arm64I16x8Addv) \
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V(Arm64I32x4Addv) \
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V(Arm64I64x2AddPair) \
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V(Arm64F32x4AddReducePairwise) \
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V(Arm64F64x2AddPair) \
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V(Arm64I32x4TruncSatF64x2SZero) \
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V(Arm64I32x4TruncSatF64x2UZero) \
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V(Arm64IExtractLaneU) \
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V(Arm64IExtractLaneS) \
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V(Arm64I16x8Shl) \
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V(Arm64I16x8ShrS) \
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V(Arm64I16x8SConvertI32x4) \
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V(Arm64I16x8Mul) \
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V(Arm64I16x8ShrU) \
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V(Arm64I16x8UConvertI32x4) \
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V(Arm64Mla) \
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V(Arm64Mls) \
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V(Arm64FAdd) \
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V(Arm64FSub) \
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V(Arm64FMul) \
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V(Arm64FMulElement) \
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V(Arm64FDiv) \
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V(Arm64FMin) \
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V(Arm64FMax) \
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V(Arm64FEq) \
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V(Arm64FNe) \
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V(Arm64FLt) \
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V(Arm64FLe) \
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V(Arm64FGt) \
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V(Arm64FGe) \
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V(Arm64IAdd) \
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V(Arm64ISub) \
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V(Arm64IEq) \
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V(Arm64INe) \
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V(Arm64IGtS) \
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V(Arm64IGeS) \
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V(Arm64ILtS) \
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V(Arm64ILeS) \
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V(Arm64IMinS) \
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V(Arm64IMaxS) \
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V(Arm64IMinU) \
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V(Arm64IMaxU) \
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V(Arm64IGtU) \
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V(Arm64IGeU) \
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V(Arm64IAddSatS) \
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V(Arm64ISubSatS) \
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V(Arm64IAddSatU) \
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V(Arm64ISubSatU) \
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V(Arm64RoundingAverageU) \
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V(Arm64Smlal) \
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V(Arm64Smlal2) \
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V(Arm64Sadalp) \
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V(Arm64Saddlp) \
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V(Arm64Bcax) \
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V(Arm64Eor3) \
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V(Arm64Uadalp) \
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V(Arm64Uaddlp) \
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V(Arm64Umlal) \
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V(Arm64Umlal2)
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#define TARGET_ARCH_OPCODE_LIST(V) \
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TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \
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V(Arm64Add) \
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V(Arm64Add32) \
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V(Arm64And) \
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V(Arm64And32) \
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V(Arm64Bic) \
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V(Arm64Bic32) \
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V(Arm64Clz) \
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V(Arm64Clz32) \
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V(Arm64Cmp) \
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V(Arm64Cmp32) \
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V(Arm64Cmn) \
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V(Arm64Cmn32) \
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V(Arm64Cnt) \
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V(Arm64Cnt32) \
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V(Arm64Cnt64) \
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V(Arm64Tst) \
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V(Arm64Tst32) \
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V(Arm64Or) \
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V(Arm64Or32) \
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V(Arm64Orn) \
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V(Arm64Orn32) \
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V(Arm64Eor) \
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V(Arm64Eor32) \
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V(Arm64Eon) \
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V(Arm64Eon32) \
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V(Arm64Sub) \
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V(Arm64Sub32) \
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V(Arm64Mul) \
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V(Arm64Mul32) \
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V(Arm64Smulh) \
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V(Arm64Smull) \
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V(Arm64Smull2) \
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V(Arm64Umull) \
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V(Arm64Umulh) \
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V(Arm64Umull2) \
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V(Arm64Madd) \
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V(Arm64Madd32) \
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V(Arm64Msub) \
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V(Arm64Msub32) \
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V(Arm64Mneg) \
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V(Arm64Mneg32) \
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V(Arm64Idiv) \
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V(Arm64Idiv32) \
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V(Arm64Udiv) \
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V(Arm64Udiv32) \
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V(Arm64Imod) \
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V(Arm64Imod32) \
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V(Arm64Umod) \
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V(Arm64Umod32) \
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V(Arm64Not) \
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V(Arm64Not32) \
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V(Arm64Lsl) \
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V(Arm64Lsl32) \
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V(Arm64Lsr) \
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V(Arm64Lsr32) \
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V(Arm64Asr) \
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V(Arm64Asr32) \
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V(Arm64Ror) \
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V(Arm64Ror32) \
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V(Arm64Mov32) \
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V(Arm64Sxtb32) \
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V(Arm64Sxth32) \
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V(Arm64Sxtb) \
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V(Arm64Sxth) \
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V(Arm64Sxtw) \
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V(Arm64Sbfx) \
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V(Arm64Sbfx32) \
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V(Arm64Ubfx) \
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V(Arm64Ubfx32) \
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V(Arm64Ubfiz32) \
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V(Arm64Sbfiz) \
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V(Arm64Bfi) \
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V(Arm64Rbit) \
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V(Arm64Rbit32) \
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V(Arm64Rev) \
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V(Arm64Rev32) \
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V(Arm64TestAndBranch32) \
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V(Arm64TestAndBranch) \
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V(Arm64CompareAndBranch32) \
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V(Arm64CompareAndBranch) \
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V(Arm64Claim) \
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V(Arm64Poke) \
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V(Arm64PokePair) \
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V(Arm64Peek) \
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V(Arm64Float16RoundDown) \
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V(Arm64Float16RoundUp) \
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V(Arm64Float16RoundTruncate) \
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V(Arm64Float16RoundTiesEven) \
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V(Arm64Float32Cmp) \
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V(Arm64Float32Add) \
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V(Arm64Float32Sub) \
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V(Arm64Float32Mul) \
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V(Arm64Float32Div) \
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V(Arm64Float32Abs) \
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V(Arm64Float32Abd) \
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V(Arm64Float32Neg) \
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V(Arm64Float32Sqrt) \
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V(Arm64Float32Fnmul) \
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V(Arm64Float32RoundDown) \
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V(Arm64Float32Max) \
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V(Arm64Float32Min) \
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V(Arm64Float64Cmp) \
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V(Arm64Float64Add) \
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V(Arm64Float64Sub) \
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V(Arm64Float64Mul) \
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V(Arm64Float64Div) \
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V(Arm64Float64Mod) \
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V(Arm64Float64Max) \
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V(Arm64Float64Min) \
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V(Arm64Float64Abs) \
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V(Arm64Float64Abd) \
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V(Arm64Float64Neg) \
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V(Arm64Float64Sqrt) \
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V(Arm64Float64Fnmul) \
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V(Arm64Float64RoundDown) \
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V(Arm64Float32RoundUp) \
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V(Arm64Float64RoundUp) \
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V(Arm64Float64RoundTiesAway) \
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V(Arm64Float32RoundTruncate) \
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V(Arm64Float64RoundTruncate) \
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V(Arm64Float32RoundTiesEven) \
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V(Arm64Float64RoundTiesEven) \
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V(Arm64Float64SilenceNaN) \
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V(Arm64Float32ToFloat64) \
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V(Arm64Float64ToFloat32) \
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V(Arm64Float64ToFloat16RawBits) \
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V(Arm64Float16RawBitsToFloat64) \
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V(Arm64Float32ToInt32) \
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V(Arm64Float64ToInt32) \
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V(Arm64Float32ToUint32) \
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V(Arm64Float64ToUint32) \
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V(Arm64Float32ToInt64) \
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V(Arm64Float64ToInt64) \
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V(Arm64Float32ToUint64) \
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V(Arm64Float64ToUint64) \
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V(Arm64Int32ToFloat32) \
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V(Arm64Int32ToFloat64) \
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V(Arm64Int64ToFloat32) \
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V(Arm64Int64ToFloat64) \
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V(Arm64Uint32ToFloat32) \
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V(Arm64Uint32ToFloat64) \
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V(Arm64Uint64ToFloat32) \
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V(Arm64Uint64ToFloat64) \
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V(Arm64Float64ExtractLowWord32) \
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V(Arm64Float64ExtractHighWord32) \
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V(Arm64Float64InsertLowWord32) \
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V(Arm64Float64InsertHighWord32) \
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V(Arm64Float64MoveU64) \
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V(Arm64U64MoveFloat64) \
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V(Arm64LdarDecompressTaggedSigned) \
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V(Arm64LdarDecompressTagged) \
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V(Arm64StlrCompressTagged) \
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V(Arm64StrIndirectPointer) \
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V(Arm64LdrDecodeSandboxedPointer) \
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V(Arm64StrEncodeSandboxedPointer) \
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V(Arm64DmbIsh) \
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V(Arm64DsbIsb) \
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V(Arm64Word64AtomicAddUint64) \
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V(Arm64Word64AtomicSubUint64) \
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V(Arm64Word64AtomicAndUint64) \
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V(Arm64Word64AtomicOrUint64) \
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V(Arm64Word64AtomicXorUint64) \
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V(Arm64Word64AtomicExchangeUint64) \
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V(Arm64Word64AtomicCompareExchangeUint64) \
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IF_WASM(TARGET_ARCH_SIMD_OPCODE_LIST, V)
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// Addressing modes represent the "shape" of inputs to an instruction.
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// Many instructions support multiple addressing modes. Addressing modes
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// are encoded into the InstructionCode of the instruction and tell the
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// code generator after register allocation which assembler method to call.
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//
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// We use the following local notation for addressing modes:
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//
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// R = register
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// O = register or stack slot
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// D = double register
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// I = immediate (handle, external, int32)
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// MRI = [register + immediate]
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// MRR = [register + register]
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#define TARGET_ADDRESSING_MODE_LIST(V) \
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V(MRI)
/* [%r0 + K] */
\
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V(MRR)
/* [%r0 + %r1] */
\
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V(Operand2_R_LSL_I)
/* %r0 LSL K */
\
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V(Operand2_R_LSR_I)
/* %r0 LSR K */
\
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V(Operand2_R_ASR_I)
/* %r0 ASR K */
\
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V(Operand2_R_ROR_I)
/* %r0 ROR K */
\
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V(Operand2_R_UXTB)
/* %r0 UXTB (unsigned extend byte) */
\
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V(Operand2_R_UXTH)
/* %r0 UXTH (unsigned extend halfword) */
\
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V(Operand2_R_SXTB)
/* %r0 SXTB (signed extend byte) */
\
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V(Operand2_R_SXTH)
/* %r0 SXTH (signed extend halfword) */
\
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V(Operand2_R_SXTW)
/* %r0 SXTW (signed extend word) */
\
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V(Root)
/* [%rr + K] */
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}
// namespace compiler
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}
// namespace internal
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}
// namespace v8
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#endif
// V8_COMPILER_BACKEND_ARM64_INSTRUCTION_CODES_ARM64_H_
v8::internal::internal
internal
Definition
wasm-objects-inl.h:458
v8
Definition
api-arguments-inl.h:19
src
compiler
backend
arm64
instruction-codes-arm64.h
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