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instruction-codes-arm.h
Go to the documentation of this file.
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// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef V8_COMPILER_BACKEND_ARM_INSTRUCTION_CODES_ARM_H_
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#define V8_COMPILER_BACKEND_ARM_INSTRUCTION_CODES_ARM_H_
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namespace
v8
{
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namespace
internal
{
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namespace
compiler {
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// ARM-specific opcodes that specify which assembly sequence to emit.
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// Most opcodes specify a single instruction.
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#define TARGET_ARCH_OPCODE_LIST(V) \
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V(ArmAdd) \
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V(ArmAnd) \
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V(ArmBic) \
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V(ArmClz) \
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V(ArmCmp) \
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V(ArmCmn) \
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V(ArmTst) \
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V(ArmTeq) \
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V(ArmOrr) \
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V(ArmEor) \
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V(ArmSub) \
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V(ArmRsb) \
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V(ArmMul) \
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V(ArmMla) \
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V(ArmMls) \
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V(ArmSmull) \
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V(ArmSmmul) \
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V(ArmSmmla) \
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V(ArmUmull) \
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V(ArmSdiv) \
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V(ArmUdiv) \
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V(ArmMov) \
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V(ArmMvn) \
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V(ArmBfc) \
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V(ArmUbfx) \
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V(ArmSbfx) \
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V(ArmSxtb) \
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V(ArmSxth) \
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V(ArmSxtab) \
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V(ArmSxtah) \
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V(ArmUxtb) \
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V(ArmUxth) \
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V(ArmUxtab) \
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V(ArmRbit) \
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V(ArmRev) \
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V(ArmUxtah) \
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V(ArmAddPair) \
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V(ArmSubPair) \
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V(ArmMulPair) \
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V(ArmLslPair) \
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V(ArmLsrPair) \
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V(ArmAsrPair) \
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V(ArmVcmpF32) \
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V(ArmVaddF32) \
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V(ArmVsubF32) \
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V(ArmVmulF32) \
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V(ArmVmlaF32) \
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V(ArmVmlsF32) \
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V(ArmVdivF32) \
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V(ArmVabsF32) \
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V(ArmVnegF32) \
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V(ArmVsqrtF32) \
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V(ArmVcmpF64) \
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V(ArmVaddF64) \
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V(ArmVsubF64) \
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V(ArmVmulF64) \
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V(ArmVmlaF64) \
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V(ArmVmlsF64) \
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V(ArmVdivF64) \
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V(ArmVmodF64) \
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V(ArmVabsF64) \
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V(ArmVnegF64) \
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V(ArmVsqrtF64) \
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V(ArmVmullLow) \
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V(ArmVmullHigh) \
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V(ArmVrintmF32) \
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V(ArmVrintmF64) \
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V(ArmVrintpF32) \
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V(ArmVrintpF64) \
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V(ArmVrintzF32) \
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V(ArmVrintzF64) \
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V(ArmVrintaF64) \
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V(ArmVrintnF32) \
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V(ArmVrintnF64) \
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V(ArmVcvtF32F64) \
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V(ArmVcvtF64F32) \
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V(ArmVcvtF32S32) \
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V(ArmVcvtF32U32) \
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V(ArmVcvtF64S32) \
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V(ArmVcvtF64U32) \
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V(ArmVcvtS32F32) \
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V(ArmVcvtU32F32) \
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V(ArmVcvtS32F64) \
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V(ArmVcvtU32F64) \
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V(ArmVmovU32F32) \
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V(ArmVmovF32U32) \
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V(ArmVmovLowU32F64) \
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V(ArmVmovLowF64U32) \
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V(ArmVmovHighU32F64) \
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V(ArmVmovHighF64U32) \
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V(ArmVmovF64U32U32) \
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V(ArmVmovU32U32F64) \
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V(ArmVldrF32) \
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V(ArmVstrF32) \
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V(ArmVldrF64) \
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V(ArmVld1F64) \
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V(ArmVstrF64) \
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V(ArmVst1F64) \
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V(ArmVld1S128) \
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V(ArmVst1S128) \
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V(ArmVcnt) \
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V(ArmVpadal) \
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V(ArmVpaddl) \
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V(ArmFloat32Max) \
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V(ArmFloat64Max) \
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V(ArmFloat32Min) \
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V(ArmFloat64Min) \
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V(ArmFloat64SilenceNaN) \
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V(ArmLdrb) \
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V(ArmLdrsb) \
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V(ArmStrb) \
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V(ArmLdrh) \
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V(ArmLdrsh) \
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V(ArmStrh) \
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V(ArmLdr) \
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V(ArmStr) \
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V(ArmPush) \
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V(ArmPoke) \
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V(ArmPeek) \
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V(ArmDmbIsh) \
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V(ArmDsbIsb) \
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V(ArmF64x2Splat) \
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V(ArmF64x2ExtractLane) \
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V(ArmF64x2ReplaceLane) \
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V(ArmF64x2Abs) \
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V(ArmF64x2Neg) \
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V(ArmF64x2Sqrt) \
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V(ArmF64x2Add) \
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V(ArmF64x2Sub) \
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V(ArmF64x2Mul) \
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V(ArmF64x2Div) \
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V(ArmF64x2Min) \
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V(ArmF64x2Max) \
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V(ArmF64x2Eq) \
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V(ArmF64x2Ne) \
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V(ArmF64x2Lt) \
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V(ArmF64x2Le) \
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V(ArmF64x2Pmin) \
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V(ArmF64x2Pmax) \
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V(ArmF64x2Qfma) \
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V(ArmF64x2Qfms) \
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V(ArmF64x2Ceil) \
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V(ArmF64x2Floor) \
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V(ArmF64x2Trunc) \
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V(ArmF64x2NearestInt) \
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V(ArmF64x2ConvertLowI32x4S) \
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V(ArmF64x2ConvertLowI32x4U) \
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V(ArmF64x2PromoteLowF32x4) \
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V(ArmF32x4Splat) \
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V(ArmF32x4ExtractLane) \
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V(ArmF32x4ReplaceLane) \
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V(ArmF32x4SConvertI32x4) \
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V(ArmF32x4UConvertI32x4) \
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V(ArmF32x4Abs) \
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V(ArmF32x4Neg) \
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V(ArmF32x4Sqrt) \
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V(ArmF32x4Add) \
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V(ArmF32x4Sub) \
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V(ArmF32x4Mul) \
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V(ArmF32x4Div) \
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V(ArmF32x4Min) \
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V(ArmF32x4Max) \
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V(ArmF32x4Eq) \
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V(ArmF32x4Ne) \
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V(ArmF32x4Lt) \
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V(ArmF32x4Le) \
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V(ArmF32x4Pmin) \
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V(ArmF32x4Pmax) \
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V(ArmF32x4Qfma) \
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V(ArmF32x4Qfms) \
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V(ArmF32x4DemoteF64x2Zero) \
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V(ArmI64x2SplatI32Pair) \
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V(ArmI64x2ReplaceLaneI32Pair) \
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V(ArmI64x2Abs) \
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V(ArmI64x2Neg) \
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V(ArmI64x2Shl) \
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V(ArmI64x2ShrS) \
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V(ArmI64x2Add) \
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V(ArmI64x2Sub) \
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V(ArmI64x2Mul) \
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V(ArmI64x2ShrU) \
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V(ArmI64x2BitMask) \
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V(ArmI64x2Eq) \
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V(ArmI64x2Ne) \
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V(ArmI64x2GtS) \
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V(ArmI64x2GeS) \
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V(ArmI64x2SConvertI32x4Low) \
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V(ArmI64x2SConvertI32x4High) \
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V(ArmI64x2UConvertI32x4Low) \
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V(ArmI64x2UConvertI32x4High) \
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V(ArmI32x4Splat) \
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V(ArmI32x4ExtractLane) \
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V(ArmI32x4ReplaceLane) \
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V(ArmI32x4SConvertF32x4) \
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V(ArmI32x4SConvertI16x8Low) \
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V(ArmI32x4SConvertI16x8High) \
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V(ArmI32x4Neg) \
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V(ArmI32x4Shl) \
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V(ArmI32x4ShrS) \
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V(ArmI32x4Add) \
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V(ArmI32x4Sub) \
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V(ArmI32x4Mul) \
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V(ArmI32x4MinS) \
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V(ArmI32x4MaxS) \
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V(ArmI32x4Eq) \
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V(ArmI32x4Ne) \
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V(ArmI32x4GtS) \
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V(ArmI32x4GeS) \
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V(ArmI32x4UConvertF32x4) \
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V(ArmI32x4UConvertI16x8Low) \
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V(ArmI32x4UConvertI16x8High) \
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V(ArmI32x4ShrU) \
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V(ArmI32x4MinU) \
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V(ArmI32x4MaxU) \
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V(ArmI32x4GtU) \
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V(ArmI32x4GeU) \
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V(ArmI32x4Abs) \
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V(ArmI32x4BitMask) \
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V(ArmI32x4DotI16x8S) \
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V(ArmI16x8DotI8x16S) \
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V(ArmI32x4DotI8x16AddS) \
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V(ArmI32x4TruncSatF64x2SZero) \
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V(ArmI32x4TruncSatF64x2UZero) \
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V(ArmI16x8Splat) \
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V(ArmI16x8ExtractLaneS) \
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V(ArmI16x8ReplaceLane) \
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V(ArmI16x8SConvertI8x16Low) \
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V(ArmI16x8SConvertI8x16High) \
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V(ArmI16x8Neg) \
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V(ArmI16x8Shl) \
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V(ArmI16x8ShrS) \
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V(ArmI16x8SConvertI32x4) \
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V(ArmI16x8Add) \
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V(ArmI16x8AddSatS) \
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V(ArmI16x8Sub) \
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V(ArmI16x8SubSatS) \
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V(ArmI16x8Mul) \
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V(ArmI16x8MinS) \
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V(ArmI16x8MaxS) \
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V(ArmI16x8Eq) \
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V(ArmI16x8Ne) \
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V(ArmI16x8GtS) \
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V(ArmI16x8GeS) \
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V(ArmI16x8ExtractLaneU) \
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V(ArmI16x8UConvertI8x16Low) \
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V(ArmI16x8UConvertI8x16High) \
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V(ArmI16x8ShrU) \
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V(ArmI16x8UConvertI32x4) \
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V(ArmI16x8AddSatU) \
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V(ArmI16x8SubSatU) \
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V(ArmI16x8MinU) \
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V(ArmI16x8MaxU) \
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V(ArmI16x8GtU) \
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V(ArmI16x8GeU) \
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V(ArmI16x8RoundingAverageU) \
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V(ArmI16x8Abs) \
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V(ArmI16x8BitMask) \
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V(ArmI16x8Q15MulRSatS) \
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V(ArmI8x16Splat) \
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V(ArmI8x16ExtractLaneS) \
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V(ArmI8x16ReplaceLane) \
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V(ArmI8x16Neg) \
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V(ArmI8x16Shl) \
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V(ArmI8x16ShrS) \
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V(ArmI8x16SConvertI16x8) \
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V(ArmI8x16Add) \
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V(ArmI8x16AddSatS) \
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V(ArmI8x16Sub) \
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V(ArmI8x16SubSatS) \
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V(ArmI8x16MinS) \
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V(ArmI8x16MaxS) \
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V(ArmI8x16Eq) \
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V(ArmI8x16Ne) \
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V(ArmI8x16GtS) \
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V(ArmI8x16GeS) \
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V(ArmI8x16ExtractLaneU) \
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V(ArmI8x16ShrU) \
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V(ArmI8x16UConvertI16x8) \
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V(ArmI8x16AddSatU) \
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V(ArmI8x16SubSatU) \
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V(ArmI8x16MinU) \
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V(ArmI8x16MaxU) \
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V(ArmI8x16GtU) \
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V(ArmI8x16GeU) \
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V(ArmI8x16RoundingAverageU) \
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V(ArmI8x16Abs) \
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V(ArmI8x16BitMask) \
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V(ArmS128Const) \
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V(ArmS128Zero) \
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V(ArmS128AllOnes) \
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V(ArmS128Dup) \
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V(ArmS128And) \
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V(ArmS128Or) \
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V(ArmS128Xor) \
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V(ArmS128Not) \
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V(ArmS128Select) \
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V(ArmS128AndNot) \
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V(ArmS32x4ZipLeft) \
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V(ArmS32x4ZipRight) \
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V(ArmS32x4UnzipLeft) \
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V(ArmS32x4UnzipRight) \
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V(ArmS32x4TransposeLeft) \
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V(ArmS32x4TransposeRight) \
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V(ArmS32x4Shuffle) \
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V(ArmS16x8ZipLeft) \
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V(ArmS16x8ZipRight) \
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V(ArmS16x8UnzipLeft) \
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V(ArmS16x8UnzipRight) \
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V(ArmS16x8TransposeLeft) \
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V(ArmS16x8TransposeRight) \
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V(ArmS8x16ZipLeft) \
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V(ArmS8x16ZipRight) \
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V(ArmS8x16UnzipLeft) \
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V(ArmS8x16UnzipRight) \
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V(ArmS8x16TransposeLeft) \
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V(ArmS8x16TransposeRight) \
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V(ArmS8x16Concat) \
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V(ArmI8x16Swizzle) \
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V(ArmI8x16Shuffle) \
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V(ArmS32x2Reverse) \
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V(ArmS16x4Reverse) \
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V(ArmS16x2Reverse) \
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V(ArmS8x8Reverse) \
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V(ArmS8x4Reverse) \
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V(ArmS8x2Reverse) \
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V(ArmI64x2AllTrue) \
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V(ArmI32x4AllTrue) \
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V(ArmI16x8AllTrue) \
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V(ArmV128AnyTrue) \
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V(ArmI8x16AllTrue) \
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V(ArmS128Load8Splat) \
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V(ArmS128Load16Splat) \
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V(ArmS128Load32Splat) \
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V(ArmS128Load64Splat) \
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V(ArmS128Load8x8S) \
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V(ArmS128Load8x8U) \
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V(ArmS128Load16x4S) \
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V(ArmS128Load16x4U) \
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V(ArmS128Load32x2S) \
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V(ArmS128Load32x2U) \
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V(ArmS128Load32Zero) \
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V(ArmS128Load64Zero) \
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V(ArmS128LoadLaneLow) \
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V(ArmS128LoadLaneHigh) \
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V(ArmS128StoreLaneLow) \
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V(ArmS128StoreLaneHigh) \
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V(ArmWord32AtomicPairLoad) \
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V(ArmWord32AtomicPairStore) \
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V(ArmWord32AtomicPairAdd) \
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V(ArmWord32AtomicPairSub) \
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V(ArmWord32AtomicPairAnd) \
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V(ArmWord32AtomicPairOr) \
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V(ArmWord32AtomicPairXor) \
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V(ArmWord32AtomicPairExchange) \
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V(ArmWord32AtomicPairCompareExchange)
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// Addressing modes represent the "shape" of inputs to an instruction.
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// Many instructions support multiple addressing modes. Addressing modes
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// are encoded into the InstructionCode of the instruction and tell the
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// code generator after register allocation which assembler method to call.
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#define TARGET_ADDRESSING_MODE_LIST(V) \
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V(Offset_RI)
/* [%r0 + K] */
\
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V(Offset_RR)
/* [%r0 + %r1] */
\
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V(Operand2_I)
/* K */
\
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V(Operand2_R)
/* %r0 */
\
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V(Operand2_R_ASR_I)
/* %r0 ASR K */
\
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V(Operand2_R_LSL_I)
/* %r0 LSL K */
\
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V(Operand2_R_LSR_I)
/* %r0 LSR K */
\
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V(Operand2_R_ROR_I)
/* %r0 ROR K */
\
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V(Operand2_R_ASR_R)
/* %r0 ASR %r1 */
\
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V(Operand2_R_LSL_R)
/* %r0 LSL %r1 */
\
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V(Operand2_R_LSR_R)
/* %r0 LSR %r1 */
\
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V(Operand2_R_ROR_R)
/* %r0 ROR %r1 */
\
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V(Root)
/* [%rr + K] */
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}
// namespace compiler
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}
// namespace internal
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}
// namespace v8
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#endif
// V8_COMPILER_BACKEND_ARM_INSTRUCTION_CODES_ARM_H_
v8::internal::internal
internal
Definition
wasm-objects-inl.h:458
v8
Definition
api-arguments-inl.h:19
src
compiler
backend
arm
instruction-codes-arm.h
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