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instruction-codes-ia32.h
Go to the documentation of this file.
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// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_
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#define V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_
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namespace
v8
{
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namespace
internal
{
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namespace
compiler {
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// IA32-specific opcodes that specify which assembly sequence to emit.
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// Most opcodes specify a single instruction.
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#define TARGET_ARCH_OPCODE_LIST(V) \
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V(IA32Add) \
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V(IA32And) \
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V(IA32Cmp) \
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V(IA32Cmp16) \
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V(IA32Cmp8) \
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V(IA32Test) \
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V(IA32Test16) \
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V(IA32Test8) \
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V(IA32Or) \
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V(IA32Xor) \
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V(IA32Sub) \
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V(IA32Imul) \
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V(IA32ImulHigh) \
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V(IA32UmulHigh) \
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V(IA32Idiv) \
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V(IA32Udiv) \
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V(IA32Not) \
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V(IA32Neg) \
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V(IA32Shl) \
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V(IA32Shr) \
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V(IA32Sar) \
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V(IA32AddPair) \
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V(IA32SubPair) \
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V(IA32MulPair) \
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V(IA32ShlPair) \
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V(IA32ShrPair) \
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V(IA32SarPair) \
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V(IA32Rol) \
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V(IA32Ror) \
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V(IA32Lzcnt) \
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V(IA32Tzcnt) \
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V(IA32Popcnt) \
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V(IA32Bswap) \
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V(IA32MFence) \
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V(IA32LFence) \
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V(IA32Float32Cmp) \
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V(IA32Float32Sqrt) \
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V(IA32Float32Round) \
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V(IA32Float64Cmp) \
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V(IA32Float64Mod) \
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V(IA32Float32Max) \
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V(IA32Float64Max) \
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V(IA32Float32Min) \
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V(IA32Float64Min) \
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V(IA32Float64Sqrt) \
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V(IA32Float64Round) \
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V(IA32Float32ToFloat64) \
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V(IA32Float64ToFloat32) \
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V(IA32Float32ToInt32) \
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V(IA32Float32ToUint32) \
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V(IA32Float64ToInt32) \
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V(IA32Float64ToUint32) \
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V(SSEInt32ToFloat32) \
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V(IA32Uint32ToFloat32) \
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V(SSEInt32ToFloat64) \
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V(IA32Uint32ToFloat64) \
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V(IA32Float64ExtractLowWord32) \
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V(IA32Float64ExtractHighWord32) \
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V(IA32Float64InsertLowWord32) \
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V(IA32Float64InsertHighWord32) \
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V(IA32Float64FromWord32Pair) \
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V(IA32Float64LoadLowWord32) \
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V(IA32Float64SilenceNaN) \
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V(Float32Add) \
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V(Float32Sub) \
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V(Float64Add) \
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V(Float64Sub) \
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V(Float32Mul) \
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V(Float32Div) \
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V(Float64Mul) \
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V(Float64Div) \
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V(Float64Abs) \
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V(Float64Neg) \
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V(Float32Abs) \
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V(Float32Neg) \
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V(IA32Movsxbl) \
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V(IA32Movzxbl) \
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V(IA32Movb) \
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V(IA32Movsxwl) \
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V(IA32Movzxwl) \
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V(IA32Movw) \
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V(IA32Movl) \
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V(IA32Movss) \
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V(IA32Movsd) \
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V(IA32Movdqu) \
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V(IA32Movlps) \
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V(IA32Movhps) \
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V(IA32BitcastFI) \
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V(IA32BitcastIF) \
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V(IA32Blendvpd) \
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V(IA32Blendvps) \
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V(IA32Lea) \
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V(IA32Pblendvb) \
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V(IA32Push) \
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V(IA32Poke) \
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V(IA32Peek) \
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V(IA32Cvttps2dq) \
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V(IA32Cvttpd2dq) \
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V(IA32I32x4TruncF32x4U) \
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V(IA32I32x4TruncF64x2UZero) \
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V(IA32F64x2Splat) \
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V(IA32F64x2ExtractLane) \
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V(IA32F64x2ReplaceLane) \
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V(IA32F64x2Sqrt) \
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V(IA32F64x2Add) \
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V(IA32F64x2Sub) \
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V(IA32F64x2Mul) \
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V(IA32F64x2Div) \
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V(IA32F64x2Min) \
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V(IA32F64x2Max) \
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V(IA32F64x2Eq) \
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V(IA32F64x2Ne) \
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V(IA32F64x2Lt) \
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V(IA32F64x2Le) \
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V(IA32F64x2Qfma) \
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V(IA32F64x2Qfms) \
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V(IA32Minpd) \
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V(IA32Maxpd) \
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V(IA32F64x2Round) \
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V(IA32F64x2ConvertLowI32x4S) \
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V(IA32F64x2ConvertLowI32x4U) \
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V(IA32F64x2PromoteLowF32x4) \
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V(IA32I64x2SplatI32Pair) \
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V(IA32I64x2ReplaceLaneI32Pair) \
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V(IA32I64x2Abs) \
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V(IA32I64x2Neg) \
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V(IA32I64x2Shl) \
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V(IA32I64x2ShrS) \
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V(IA32I64x2Add) \
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V(IA32I64x2Sub) \
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V(IA32I64x2Mul) \
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V(IA32I64x2ShrU) \
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V(IA32I64x2BitMask) \
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V(IA32I64x2Eq) \
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V(IA32I64x2Ne) \
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V(IA32I64x2GtS) \
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V(IA32I64x2GeS) \
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V(IA32I64x2ExtMulLowI32x4S) \
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V(IA32I64x2ExtMulHighI32x4S) \
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V(IA32I64x2ExtMulLowI32x4U) \
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V(IA32I64x2ExtMulHighI32x4U) \
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V(IA32I64x2SConvertI32x4Low) \
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V(IA32I64x2SConvertI32x4High) \
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V(IA32I64x2UConvertI32x4Low) \
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V(IA32I64x2UConvertI32x4High) \
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V(IA32F32x4Splat) \
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V(IA32F32x4ExtractLane) \
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V(IA32Insertps) \
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V(IA32F32x4SConvertI32x4) \
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V(IA32F32x4UConvertI32x4) \
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V(IA32F32x4Sqrt) \
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V(IA32F32x4Add) \
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V(IA32F32x4Sub) \
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V(IA32F32x4Mul) \
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V(IA32F32x4Div) \
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V(IA32F32x4Min) \
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V(IA32F32x4Max) \
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V(IA32F32x4Eq) \
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V(IA32F32x4Ne) \
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V(IA32F32x4Lt) \
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V(IA32F32x4Le) \
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V(IA32F32x4Qfma) \
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V(IA32F32x4Qfms) \
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V(IA32Minps) \
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V(IA32Maxps) \
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V(IA32F32x4Round) \
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V(IA32F32x4DemoteF64x2Zero) \
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V(IA32I32x4Splat) \
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V(IA32I32x4ExtractLane) \
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V(IA32I32x4SConvertF32x4) \
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V(IA32I32x4SConvertI16x8Low) \
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V(IA32I32x4SConvertI16x8High) \
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V(IA32I32x4Neg) \
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V(IA32I32x4Shl) \
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V(IA32I32x4ShrS) \
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V(IA32I32x4Add) \
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V(IA32I32x4Sub) \
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V(IA32I32x4Mul) \
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V(IA32I32x4MinS) \
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V(IA32I32x4MaxS) \
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V(IA32I32x4Eq) \
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V(IA32I32x4Ne) \
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V(IA32I32x4GtS) \
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V(IA32I32x4GeS) \
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V(SSEI32x4UConvertF32x4) \
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V(AVXI32x4UConvertF32x4) \
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V(IA32I32x4UConvertI16x8Low) \
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V(IA32I32x4UConvertI16x8High) \
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V(IA32I32x4ShrU) \
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V(IA32I32x4MinU) \
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V(IA32I32x4MaxU) \
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V(SSEI32x4GtU) \
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V(AVXI32x4GtU) \
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V(SSEI32x4GeU) \
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V(AVXI32x4GeU) \
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V(IA32I32x4Abs) \
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V(IA32I32x4BitMask) \
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V(IA32I32x4DotI16x8S) \
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V(IA32I32x4DotI8x16I7x16AddS) \
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V(IA32I32x4ExtMulLowI16x8S) \
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V(IA32I32x4ExtMulHighI16x8S) \
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V(IA32I32x4ExtMulLowI16x8U) \
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V(IA32I32x4ExtMulHighI16x8U) \
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V(IA32I32x4ExtAddPairwiseI16x8S) \
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V(IA32I32x4ExtAddPairwiseI16x8U) \
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V(IA32I32x4TruncSatF64x2SZero) \
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V(IA32I32x4TruncSatF64x2UZero) \
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V(IA32I16x8Splat) \
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V(IA32I16x8ExtractLaneS) \
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V(IA32I16x8SConvertI8x16Low) \
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V(IA32I16x8SConvertI8x16High) \
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V(IA32I16x8Neg) \
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V(IA32I16x8Shl) \
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V(IA32I16x8ShrS) \
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V(IA32I16x8SConvertI32x4) \
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V(IA32I16x8Add) \
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V(IA32I16x8AddSatS) \
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V(IA32I16x8Sub) \
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V(IA32I16x8SubSatS) \
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V(IA32I16x8Mul) \
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V(IA32I16x8MinS) \
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V(IA32I16x8MaxS) \
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V(IA32I16x8Eq) \
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V(SSEI16x8Ne) \
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V(AVXI16x8Ne) \
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V(IA32I16x8GtS) \
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V(SSEI16x8GeS) \
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V(AVXI16x8GeS) \
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V(IA32I16x8UConvertI8x16Low) \
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V(IA32I16x8UConvertI8x16High) \
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V(IA32I16x8ShrU) \
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V(IA32I16x8UConvertI32x4) \
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V(IA32I16x8AddSatU) \
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V(IA32I16x8SubSatU) \
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V(IA32I16x8MinU) \
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V(IA32I16x8MaxU) \
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V(SSEI16x8GtU) \
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V(AVXI16x8GtU) \
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V(SSEI16x8GeU) \
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V(AVXI16x8GeU) \
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V(IA32I16x8RoundingAverageU) \
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V(IA32I16x8Abs) \
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V(IA32I16x8BitMask) \
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V(IA32I16x8ExtMulLowI8x16S) \
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V(IA32I16x8ExtMulHighI8x16S) \
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V(IA32I16x8ExtMulLowI8x16U) \
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V(IA32I16x8ExtMulHighI8x16U) \
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V(IA32I16x8ExtAddPairwiseI8x16S) \
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V(IA32I16x8ExtAddPairwiseI8x16U) \
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V(IA32I16x8Q15MulRSatS) \
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V(IA32I16x8RelaxedQ15MulRS) \
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V(IA32I8x16Splat) \
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V(IA32I8x16ExtractLaneS) \
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V(IA32Pinsrb) \
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V(IA32Pinsrw) \
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V(IA32Pinsrd) \
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V(IA32Pextrb) \
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V(IA32Pextrw) \
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V(IA32S128Store32Lane) \
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V(IA32I8x16SConvertI16x8) \
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V(IA32I8x16Neg) \
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V(IA32I8x16Shl) \
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V(IA32I8x16ShrS) \
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V(IA32I8x16Add) \
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V(IA32I8x16AddSatS) \
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V(IA32I8x16Sub) \
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V(IA32I8x16SubSatS) \
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V(IA32I8x16MinS) \
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V(IA32I8x16MaxS) \
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V(IA32I8x16Eq) \
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V(SSEI8x16Ne) \
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V(AVXI8x16Ne) \
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V(IA32I8x16GtS) \
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V(SSEI8x16GeS) \
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V(AVXI8x16GeS) \
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V(IA32I8x16UConvertI16x8) \
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V(IA32I8x16AddSatU) \
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V(IA32I8x16SubSatU) \
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V(IA32I8x16ShrU) \
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V(IA32I8x16MinU) \
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V(IA32I8x16MaxU) \
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V(SSEI8x16GtU) \
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V(AVXI8x16GtU) \
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V(SSEI8x16GeU) \
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V(AVXI8x16GeU) \
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V(IA32I8x16RoundingAverageU) \
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V(IA32I8x16Abs) \
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V(IA32I8x16BitMask) \
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V(IA32I8x16Popcnt) \
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V(IA32S128Const) \
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V(IA32S128Zero) \
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V(IA32S128AllOnes) \
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V(IA32S128Not) \
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V(IA32S128And) \
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V(IA32S128Or) \
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V(IA32S128Xor) \
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V(IA32S128Select) \
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V(IA32S128AndNot) \
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V(IA32I8x16Swizzle) \
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V(IA32I8x16Shuffle) \
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V(IA32S128Load8Splat) \
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V(IA32S128Load16Splat) \
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V(IA32S128Load32Splat) \
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V(IA32S128Load64Splat) \
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V(IA32S128Load8x8S) \
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V(IA32S128Load8x8U) \
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V(IA32S128Load16x4S) \
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V(IA32S128Load16x4U) \
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V(IA32S128Load32x2S) \
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V(IA32S128Load32x2U) \
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V(IA32S32x4Rotate) \
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V(IA32S32x4Swizzle) \
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V(IA32S32x4Shuffle) \
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V(IA32S16x8Blend) \
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V(IA32S16x8HalfShuffle1) \
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V(IA32S16x8HalfShuffle2) \
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V(IA32S8x16Alignr) \
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V(IA32S16x8Dup) \
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V(IA32S8x16Dup) \
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V(SSES16x8UnzipHigh) \
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V(AVXS16x8UnzipHigh) \
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V(SSES16x8UnzipLow) \
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V(AVXS16x8UnzipLow) \
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V(SSES8x16UnzipHigh) \
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V(AVXS8x16UnzipHigh) \
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V(SSES8x16UnzipLow) \
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V(AVXS8x16UnzipLow) \
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V(IA32S64x2UnpackHigh) \
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V(IA32S32x4UnpackHigh) \
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V(IA32S16x8UnpackHigh) \
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V(IA32S8x16UnpackHigh) \
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V(IA32S64x2UnpackLow) \
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V(IA32S32x4UnpackLow) \
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V(IA32S16x8UnpackLow) \
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V(IA32S8x16UnpackLow) \
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V(SSES8x16TransposeLow) \
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V(AVXS8x16TransposeLow) \
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V(SSES8x16TransposeHigh) \
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V(AVXS8x16TransposeHigh) \
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V(SSES8x8Reverse) \
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V(AVXS8x8Reverse) \
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V(SSES8x4Reverse) \
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V(AVXS8x4Reverse) \
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V(SSES8x2Reverse) \
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V(AVXS8x2Reverse) \
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V(IA32S128AnyTrue) \
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V(IA32I64x2AllTrue) \
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V(IA32I32x4AllTrue) \
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V(IA32I16x8AllTrue) \
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V(IA32I8x16AllTrue) \
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V(IA32I16x8DotI8x16I7x16S) \
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V(IA32Word32AtomicPairLoad) \
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V(IA32Word32ReleasePairStore) \
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V(IA32Word32SeqCstPairStore) \
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V(IA32Word32AtomicPairAdd) \
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V(IA32Word32AtomicPairSub) \
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V(IA32Word32AtomicPairAnd) \
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V(IA32Word32AtomicPairOr) \
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V(IA32Word32AtomicPairXor) \
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V(IA32Word32AtomicPairExchange) \
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V(IA32Word32AtomicPairCompareExchange)
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// Addressing modes represent the "shape" of inputs to an instruction.
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// Many instructions support multiple addressing modes. Addressing modes
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// are encoded into the InstructionCode of the instruction and tell the
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// code generator after register allocation which assembler method to call.
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//
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// We use the following local notation for addressing modes:
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//
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// M = memory operand
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// R = base register
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// N = index register * N for N in {1, 2, 4, 8}
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// I = immediate displacement (int32_t)
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#define TARGET_ADDRESSING_MODE_LIST(V) \
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V(MR)
/* [%r1 ] */
\
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V(MRI)
/* [%r1 + K] */
\
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V(MR1)
/* [%r1 + %r2*1 ] */
\
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V(MR2)
/* [%r1 + %r2*2 ] */
\
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V(MR4)
/* [%r1 + %r2*4 ] */
\
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V(MR8)
/* [%r1 + %r2*8 ] */
\
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V(MR1I)
/* [%r1 + %r2*1 + K] */
\
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V(MR2I)
/* [%r1 + %r2*2 + K] */
\
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V(MR4I)
/* [%r1 + %r2*4 + K] */
\
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V(MR8I)
/* [%r1 + %r2*8 + K] */
\
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V(M1)
/* [ %r2*1 ] */
\
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V(M2)
/* [ %r2*2 ] */
\
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V(M4)
/* [ %r2*4 ] */
\
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V(M8)
/* [ %r2*8 ] */
\
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V(M1I)
/* [ %r2*1 + K] */
\
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V(M2I)
/* [ %r2*2 + K] */
\
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V(M4I)
/* [ %r2*4 + K] */
\
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V(M8I)
/* [ %r2*8 + K] */
\
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V(MI)
/* [ K] */
\
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V(Root)
/* [%root + K] */
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}
// namespace compiler
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}
// namespace internal
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}
// namespace v8
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#endif
// V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_
v8::internal::internal
internal
Definition
wasm-objects-inl.h:458
v8
Definition
api-arguments-inl.h:19
src
compiler
backend
ia32
instruction-codes-ia32.h
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