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instruction-codes-ppc.h
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1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_BACKEND_PPC_INSTRUCTION_CODES_PPC_H_
6#define V8_COMPILER_BACKEND_PPC_INSTRUCTION_CODES_PPC_H_
7
8namespace v8 {
9namespace internal {
10namespace compiler {
11
12// PPC-specific opcodes that specify which assembly sequence to emit.
13// Most opcodes specify a single instruction.
14
15#define TARGET_ARCH_OPCODE_LIST(V) \
16 V(PPC_Peek) \
17 V(PPC_Sync) \
18 V(PPC_And) \
19 V(PPC_AndComplement) \
20 V(PPC_Or) \
21 V(PPC_OrComplement) \
22 V(PPC_Xor) \
23 V(PPC_ShiftLeft32) \
24 V(PPC_ShiftLeft64) \
25 V(PPC_ShiftLeftPair) \
26 V(PPC_ShiftRight32) \
27 V(PPC_ShiftRight64) \
28 V(PPC_ShiftRightPair) \
29 V(PPC_ShiftRightAlg32) \
30 V(PPC_ShiftRightAlg64) \
31 V(PPC_ShiftRightAlgPair) \
32 V(PPC_RotRight32) \
33 V(PPC_RotRight64) \
34 V(PPC_Not) \
35 V(PPC_RotLeftAndMask32) \
36 V(PPC_RotLeftAndClear64) \
37 V(PPC_RotLeftAndClearLeft64) \
38 V(PPC_RotLeftAndClearRight64) \
39 V(PPC_Add32) \
40 V(PPC_Add64) \
41 V(PPC_AddWithOverflow32) \
42 V(PPC_AddPair) \
43 V(PPC_AddDouble) \
44 V(PPC_Sub) \
45 V(PPC_SubWithOverflow32) \
46 V(PPC_SubPair) \
47 V(PPC_SubDouble) \
48 V(PPC_Mul32) \
49 V(PPC_Mul32WithHigh32) \
50 V(PPC_Mul64) \
51 V(PPC_MulHighS64) \
52 V(PPC_MulHighU64) \
53 V(PPC_MulHigh32) \
54 V(PPC_MulHighU32) \
55 V(PPC_MulPair) \
56 V(PPC_MulDouble) \
57 V(PPC_Div32) \
58 V(PPC_Div64) \
59 V(PPC_DivU32) \
60 V(PPC_DivU64) \
61 V(PPC_DivDouble) \
62 V(PPC_Mod32) \
63 V(PPC_Mod64) \
64 V(PPC_ModU32) \
65 V(PPC_ModU64) \
66 V(PPC_ModDouble) \
67 V(PPC_Neg) \
68 V(PPC_NegDouble) \
69 V(PPC_SqrtDouble) \
70 V(PPC_FloorDouble) \
71 V(PPC_CeilDouble) \
72 V(PPC_TruncateDouble) \
73 V(PPC_RoundDouble) \
74 V(PPC_MaxDouble) \
75 V(PPC_MinDouble) \
76 V(PPC_AbsDouble) \
77 V(PPC_Cntlz32) \
78 V(PPC_Cntlz64) \
79 V(PPC_Popcnt32) \
80 V(PPC_Popcnt64) \
81 V(PPC_Cmp32) \
82 V(PPC_Cmp64) \
83 V(PPC_CmpDouble) \
84 V(PPC_Tst32) \
85 V(PPC_Tst64) \
86 V(PPC_Push) \
87 V(PPC_PushFrame) \
88 V(PPC_StoreToStackSlot) \
89 V(PPC_ExtendSignWord8) \
90 V(PPC_ExtendSignWord16) \
91 V(PPC_ExtendSignWord32) \
92 V(PPC_Uint32ToUint64) \
93 V(PPC_Int64ToInt32) \
94 V(PPC_Int64ToFloat32) \
95 V(PPC_Int64ToDouble) \
96 V(PPC_Uint64ToFloat32) \
97 V(PPC_Uint64ToDouble) \
98 V(PPC_Int32ToFloat32) \
99 V(PPC_Int32ToDouble) \
100 V(PPC_Uint32ToFloat32) \
101 V(PPC_Float32ToInt32) \
102 V(PPC_Float32ToUint32) \
103 V(PPC_Uint32ToDouble) \
104 V(PPC_Float32ToDouble) \
105 V(PPC_Float64SilenceNaN) \
106 V(PPC_DoubleToInt32) \
107 V(PPC_DoubleToUint32) \
108 V(PPC_DoubleToInt64) \
109 V(PPC_DoubleToUint64) \
110 V(PPC_DoubleToFloat32) \
111 V(PPC_DoubleExtractLowWord32) \
112 V(PPC_DoubleExtractHighWord32) \
113 V(PPC_DoubleFromWord32Pair) \
114 V(PPC_DoubleInsertLowWord32) \
115 V(PPC_DoubleInsertHighWord32) \
116 V(PPC_DoubleConstruct) \
117 V(PPC_BitcastInt32ToFloat32) \
118 V(PPC_BitcastFloat32ToInt32) \
119 V(PPC_BitcastInt64ToDouble) \
120 V(PPC_BitcastDoubleToInt64) \
121 V(PPC_LoadWordS8) \
122 V(PPC_LoadWordU8) \
123 V(PPC_LoadWordS16) \
124 V(PPC_LoadWordU16) \
125 V(PPC_LoadWordS32) \
126 V(PPC_LoadWordU32) \
127 V(PPC_LoadByteRev32) \
128 V(PPC_LoadWord64) \
129 V(PPC_LoadByteRev64) \
130 V(PPC_LoadFloat32) \
131 V(PPC_LoadDouble) \
132 V(PPC_LoadSimd128) \
133 V(PPC_LoadReverseSimd128RR) \
134 V(PPC_StoreWord8) \
135 V(PPC_StoreWord16) \
136 V(PPC_StoreWord32) \
137 V(PPC_StoreByteRev32) \
138 V(PPC_StoreWord64) \
139 V(PPC_StoreByteRev64) \
140 V(PPC_StoreFloat32) \
141 V(PPC_StoreDouble) \
142 V(PPC_StoreSimd128) \
143 V(PPC_ByteRev32) \
144 V(PPC_ByteRev64) \
145 V(PPC_AtomicExchangeUint8) \
146 V(PPC_AtomicExchangeUint16) \
147 V(PPC_AtomicExchangeWord32) \
148 V(PPC_AtomicExchangeWord64) \
149 V(PPC_AtomicCompareExchangeUint8) \
150 V(PPC_AtomicCompareExchangeUint16) \
151 V(PPC_AtomicCompareExchangeWord32) \
152 V(PPC_AtomicCompareExchangeWord64) \
153 V(PPC_AtomicAddUint8) \
154 V(PPC_AtomicAddUint16) \
155 V(PPC_AtomicAddUint32) \
156 V(PPC_AtomicAddUint64) \
157 V(PPC_AtomicAddInt8) \
158 V(PPC_AtomicAddInt16) \
159 V(PPC_AtomicAddInt32) \
160 V(PPC_AtomicAddInt64) \
161 V(PPC_AtomicSubUint8) \
162 V(PPC_AtomicSubUint16) \
163 V(PPC_AtomicSubUint32) \
164 V(PPC_AtomicSubUint64) \
165 V(PPC_AtomicSubInt8) \
166 V(PPC_AtomicSubInt16) \
167 V(PPC_AtomicSubInt32) \
168 V(PPC_AtomicSubInt64) \
169 V(PPC_AtomicAndUint8) \
170 V(PPC_AtomicAndUint16) \
171 V(PPC_AtomicAndUint32) \
172 V(PPC_AtomicAndUint64) \
173 V(PPC_AtomicAndInt8) \
174 V(PPC_AtomicAndInt16) \
175 V(PPC_AtomicAndInt32) \
176 V(PPC_AtomicAndInt64) \
177 V(PPC_AtomicOrUint8) \
178 V(PPC_AtomicOrUint16) \
179 V(PPC_AtomicOrUint32) \
180 V(PPC_AtomicOrUint64) \
181 V(PPC_AtomicOrInt8) \
182 V(PPC_AtomicOrInt16) \
183 V(PPC_AtomicOrInt32) \
184 V(PPC_AtomicOrInt64) \
185 V(PPC_AtomicXorUint8) \
186 V(PPC_AtomicXorUint16) \
187 V(PPC_AtomicXorUint32) \
188 V(PPC_AtomicXorUint64) \
189 V(PPC_AtomicXorInt8) \
190 V(PPC_AtomicXorInt16) \
191 V(PPC_AtomicXorInt32) \
192 V(PPC_AtomicXorInt64) \
193 V(PPC_F64x2Add) \
194 V(PPC_F64x2Sub) \
195 V(PPC_F64x2Mul) \
196 V(PPC_F64x2Eq) \
197 V(PPC_F64x2Ne) \
198 V(PPC_F64x2Le) \
199 V(PPC_F64x2Lt) \
200 V(PPC_F64x2Abs) \
201 V(PPC_F64x2Neg) \
202 V(PPC_F64x2Sqrt) \
203 V(PPC_F64x2Qfma) \
204 V(PPC_F64x2Qfms) \
205 V(PPC_F64x2Div) \
206 V(PPC_F64x2Min) \
207 V(PPC_F64x2Max) \
208 V(PPC_F64x2Ceil) \
209 V(PPC_F64x2Floor) \
210 V(PPC_F64x2Trunc) \
211 V(PPC_F64x2Pmin) \
212 V(PPC_F64x2Pmax) \
213 V(PPC_F64x2ConvertLowI32x4S) \
214 V(PPC_F64x2ConvertLowI32x4U) \
215 V(PPC_F64x2PromoteLowF32x4) \
216 V(PPC_F32x4Add) \
217 V(PPC_F32x4Sub) \
218 V(PPC_F32x4Mul) \
219 V(PPC_F32x4Eq) \
220 V(PPC_F32x4Ne) \
221 V(PPC_F32x4Lt) \
222 V(PPC_F32x4Le) \
223 V(PPC_F32x4Abs) \
224 V(PPC_F32x4Neg) \
225 V(PPC_F32x4Sqrt) \
226 V(PPC_F32x4SConvertI32x4) \
227 V(PPC_F32x4UConvertI32x4) \
228 V(PPC_F32x4Div) \
229 V(PPC_F32x4Min) \
230 V(PPC_F32x4Max) \
231 V(PPC_F32x4Ceil) \
232 V(PPC_F32x4Floor) \
233 V(PPC_F32x4Trunc) \
234 V(PPC_F32x4Pmin) \
235 V(PPC_F32x4Pmax) \
236 V(PPC_F32x4Qfma) \
237 V(PPC_F32x4Qfms) \
238 V(PPC_F32x4DemoteF64x2Zero) \
239 V(PPC_I64x2Add) \
240 V(PPC_I64x2Sub) \
241 V(PPC_I64x2Mul) \
242 V(PPC_I64x2Eq) \
243 V(PPC_I64x2Ne) \
244 V(PPC_I64x2GtS) \
245 V(PPC_I64x2GeS) \
246 V(PPC_I64x2Shl) \
247 V(PPC_I64x2ShrS) \
248 V(PPC_I64x2ShrU) \
249 V(PPC_I64x2Neg) \
250 V(PPC_I64x2BitMask) \
251 V(PPC_I64x2SConvertI32x4Low) \
252 V(PPC_I64x2SConvertI32x4High) \
253 V(PPC_I64x2UConvertI32x4Low) \
254 V(PPC_I64x2UConvertI32x4High) \
255 V(PPC_I64x2ExtMulLowI32x4S) \
256 V(PPC_I64x2ExtMulHighI32x4S) \
257 V(PPC_I64x2ExtMulLowI32x4U) \
258 V(PPC_I64x2ExtMulHighI32x4U) \
259 V(PPC_I64x2Abs) \
260 V(PPC_I32x4Add) \
261 V(PPC_I32x4Sub) \
262 V(PPC_I32x4Mul) \
263 V(PPC_I32x4MinS) \
264 V(PPC_I32x4MinU) \
265 V(PPC_I32x4MaxS) \
266 V(PPC_I32x4MaxU) \
267 V(PPC_I32x4Eq) \
268 V(PPC_I32x4Ne) \
269 V(PPC_I32x4GtS) \
270 V(PPC_I32x4GeS) \
271 V(PPC_I32x4GtU) \
272 V(PPC_I32x4GeU) \
273 V(PPC_I32x4Shl) \
274 V(PPC_I32x4ShrS) \
275 V(PPC_I32x4ShrU) \
276 V(PPC_I32x4Neg) \
277 V(PPC_I32x4Abs) \
278 V(PPC_I32x4SConvertF32x4) \
279 V(PPC_I32x4UConvertF32x4) \
280 V(PPC_I32x4SConvertI16x8Low) \
281 V(PPC_I32x4SConvertI16x8High) \
282 V(PPC_I32x4UConvertI16x8Low) \
283 V(PPC_I32x4UConvertI16x8High) \
284 V(PPC_I32x4BitMask) \
285 V(PPC_I32x4DotI16x8S) \
286 V(PPC_I32x4ExtAddPairwiseI16x8S) \
287 V(PPC_I32x4ExtAddPairwiseI16x8U) \
288 V(PPC_I32x4ExtMulLowI16x8S) \
289 V(PPC_I32x4ExtMulHighI16x8S) \
290 V(PPC_I32x4ExtMulLowI16x8U) \
291 V(PPC_I32x4ExtMulHighI16x8U) \
292 V(PPC_I32x4TruncSatF64x2SZero) \
293 V(PPC_I32x4TruncSatF64x2UZero) \
294 V(PPC_I32x4DotI8x16AddS) \
295 V(PPC_I16x8Add) \
296 V(PPC_I16x8Sub) \
297 V(PPC_I16x8Mul) \
298 V(PPC_I16x8MinS) \
299 V(PPC_I16x8MinU) \
300 V(PPC_I16x8MaxS) \
301 V(PPC_I16x8MaxU) \
302 V(PPC_I16x8Eq) \
303 V(PPC_I16x8Ne) \
304 V(PPC_I16x8GtS) \
305 V(PPC_I16x8GeS) \
306 V(PPC_I16x8GtU) \
307 V(PPC_I16x8GeU) \
308 V(PPC_I16x8Shl) \
309 V(PPC_I16x8ShrS) \
310 V(PPC_I16x8ShrU) \
311 V(PPC_I16x8Neg) \
312 V(PPC_I16x8Abs) \
313 V(PPC_I16x8SConvertI32x4) \
314 V(PPC_I16x8UConvertI32x4) \
315 V(PPC_I16x8SConvertI8x16Low) \
316 V(PPC_I16x8SConvertI8x16High) \
317 V(PPC_I16x8UConvertI8x16Low) \
318 V(PPC_I16x8UConvertI8x16High) \
319 V(PPC_I16x8AddSatS) \
320 V(PPC_I16x8SubSatS) \
321 V(PPC_I16x8AddSatU) \
322 V(PPC_I16x8SubSatU) \
323 V(PPC_I16x8RoundingAverageU) \
324 V(PPC_I16x8BitMask) \
325 V(PPC_I16x8ExtAddPairwiseI8x16S) \
326 V(PPC_I16x8ExtAddPairwiseI8x16U) \
327 V(PPC_I16x8Q15MulRSatS) \
328 V(PPC_I16x8ExtMulLowI8x16S) \
329 V(PPC_I16x8ExtMulHighI8x16S) \
330 V(PPC_I16x8ExtMulLowI8x16U) \
331 V(PPC_I16x8ExtMulHighI8x16U) \
332 V(PPC_I16x8DotI8x16S) \
333 V(PPC_I8x16Add) \
334 V(PPC_I8x16Sub) \
335 V(PPC_I8x16MinS) \
336 V(PPC_I8x16MinU) \
337 V(PPC_I8x16MaxS) \
338 V(PPC_I8x16MaxU) \
339 V(PPC_I8x16Eq) \
340 V(PPC_I8x16Ne) \
341 V(PPC_I8x16GtS) \
342 V(PPC_I8x16GeS) \
343 V(PPC_I8x16GtU) \
344 V(PPC_I8x16GeU) \
345 V(PPC_I8x16Shl) \
346 V(PPC_I8x16ShrS) \
347 V(PPC_I8x16ShrU) \
348 V(PPC_I8x16Neg) \
349 V(PPC_I8x16Abs) \
350 V(PPC_I8x16SConvertI16x8) \
351 V(PPC_I8x16UConvertI16x8) \
352 V(PPC_I8x16AddSatS) \
353 V(PPC_I8x16SubSatS) \
354 V(PPC_I8x16AddSatU) \
355 V(PPC_I8x16SubSatU) \
356 V(PPC_I8x16RoundingAverageU) \
357 V(PPC_I8x16Shuffle) \
358 V(PPC_I8x16Swizzle) \
359 V(PPC_I8x16BitMask) \
360 V(PPC_I8x16Popcnt) \
361 V(PPC_I64x2AllTrue) \
362 V(PPC_I32x4AllTrue) \
363 V(PPC_I16x8AllTrue) \
364 V(PPC_I8x16AllTrue) \
365 V(PPC_V128AnyTrue) \
366 V(PPC_S128And) \
367 V(PPC_S128Or) \
368 V(PPC_S128Xor) \
369 V(PPC_S128Const) \
370 V(PPC_S128Zero) \
371 V(PPC_S128AllOnes) \
372 V(PPC_S128Not) \
373 V(PPC_S128Select) \
374 V(PPC_S128AndNot) \
375 V(PPC_S128Load8Splat) \
376 V(PPC_S128Load16Splat) \
377 V(PPC_S128Load32Splat) \
378 V(PPC_S128Load64Splat) \
379 V(PPC_S128Load8x8S) \
380 V(PPC_S128Load8x8U) \
381 V(PPC_S128Load16x4S) \
382 V(PPC_S128Load16x4U) \
383 V(PPC_S128Load32x2S) \
384 V(PPC_S128Load32x2U) \
385 V(PPC_S128Load32Zero) \
386 V(PPC_S128Load64Zero) \
387 V(PPC_S128Load8Lane) \
388 V(PPC_S128Load16Lane) \
389 V(PPC_S128Load32Lane) \
390 V(PPC_S128Load64Lane) \
391 V(PPC_S128Store8Lane) \
392 V(PPC_S128Store16Lane) \
393 V(PPC_S128Store32Lane) \
394 V(PPC_S128Store64Lane) \
395 V(PPC_FExtractLane) \
396 V(PPC_IExtractLane) \
397 V(PPC_IExtractLaneU) \
398 V(PPC_IExtractLaneS) \
399 V(PPC_FReplaceLane) \
400 V(PPC_IReplaceLane) \
401 V(PPC_FSplat) \
402 V(PPC_ISplat) \
403 V(PPC_StoreCompressTagged) \
404 V(PPC_StoreIndirectPointer) \
405 V(PPC_LoadDecodeSandboxedPointer) \
406 V(PPC_StoreEncodeSandboxedPointer) \
407 V(PPC_LoadDecompressTaggedSigned) \
408 V(PPC_LoadDecompressTagged)
409
410// Addressing modes represent the "shape" of inputs to an instruction.
411// Many instructions support multiple addressing modes. Addressing modes
412// are encoded into the InstructionCode of the instruction and tell the
413// code generator after register allocation which assembler method to call.
414//
415// We use the following local notation for addressing modes:
416//
417// R = register
418// O = register or stack slot
419// D = double register
420// I = immediate (handle, external, int32)
421// MRI = [register + immediate]
422// MRR = [register + register]
423#define TARGET_ADDRESSING_MODE_LIST(V) \
424 V(MRI) /* [%r0 + K] */ \
425 V(MRR) /* [%r0 + %r1] */ \
426 V(Root) /* [%rr + K] */
427
428} // namespace compiler
429} // namespace internal
430} // namespace v8
431
432#endif // V8_COMPILER_BACKEND_PPC_INSTRUCTION_CODES_PPC_H_