v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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liftoff-assembler-defs.h
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1// Copyright 2017 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_WASM_BASELINE_LIFTOFF_ASSEMBLER_DEFS_H_
6#define V8_WASM_BASELINE_LIFTOFF_ASSEMBLER_DEFS_H_
7
10
11namespace v8 {
12namespace internal {
13namespace wasm {
14
15#if V8_TARGET_ARCH_IA32
16
17// Omit ebx, which is the root register.
18constexpr RegList kLiftoffAssemblerGpCacheRegs = {eax, ecx, edx, esi, edi};
19
20// Omit xmm7, which is the kScratchDoubleReg.
21// Omit xmm0, which is not an allocatable register (see register-ia32.h).
22constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {xmm1, xmm2, xmm3,
23 xmm4, xmm5, xmm6};
24
25// For the "WasmLiftoffFrameSetup" builtin.
26constexpr Register kLiftoffFrameSetupFunctionReg = edi;
27
28#elif V8_TARGET_ARCH_X64
29
30// r10: kScratchRegister (MacroAssembler)
31// r11: kScratchRegister2 (Liftoff)
32// r13: kRootRegister
33// r14: kPtrComprCageBaseRegister
34constexpr RegList kLiftoffAssemblerGpCacheRegs = {rax, rcx, rdx, rbx, rsi,
35 rdi, r8, r9, r12, r15};
36
37constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {xmm0, xmm1, xmm2, xmm3,
38 xmm4, xmm5, xmm6, xmm7};
39
40// For the "WasmLiftoffFrameSetup" builtin.
41constexpr Register kLiftoffFrameSetupFunctionReg = r12;
42
43#elif V8_TARGET_ARCH_MIPS
44
45constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, t0, t1, t2,
46 t3, t4, t5, t6, s7, v0, v1};
47
49 f0, f2, f4, f6, f8, f10, f12, f14, f16, f18, f20, f22, f24};
50
51#elif V8_TARGET_ARCH_MIPS64
52
53constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5, a6,
54 a7, t0, t1, t2, s7, v0, v1};
55
57 f0, f2, f4, f6, f8, f10, f12, f14, f16, f18, f20, f22, f24, f26};
58
59// For the "WasmLiftoffFrameSetup" builtin.
60constexpr Register kLiftoffFrameSetupFunctionReg = t0;
61
62#elif V8_TARGET_ARCH_LOONG64
63
64// t6-t8 and s3-s4: scratch registers, s6: root
65// s8: pointer-compression-cage base
66constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5, a6,
67 a7, t0, t1, t2, t3, t4, t5,
68 s0, s1, s2, s5, s7};
69
70// f29: zero, f30-f31: macro-assembler scratch float Registers.
72 f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14,
73 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26, f27, f28};
74
75// For the "WasmLiftoffFrameSetup" builtin.
76constexpr Register kLiftoffFrameSetupFunctionReg = t0;
77
78#elif V8_TARGET_ARCH_ARM
79
80// r10: root, r11: fp, r12: ip, r13: sp, r14: lr, r15: pc.
81constexpr RegList kLiftoffAssemblerGpCacheRegs = {r0, r1, r2, r3, r4,
82 r5, r6, r7, r8, r9};
83
84// d13: zero, d14-d15: scratch
86 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12};
87
88// For the "WasmLiftoffFrameSetup" builtin.
89constexpr Register kLiftoffFrameSetupFunctionReg = r4;
90
91#elif V8_TARGET_ARCH_ARM64
92
93// x16: ip0, x17: ip1, x18: platform register, x26: root, x28: base, x29: fp,
94// x30: lr, x31: xzr.
96 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11,
97 x12, x13, x14, x15, x19, x20, x21, x22, x23, x24, x25, x27};
98
99// d15: fp_zero, d28-d31: not allocatable registers, d30-d31: macro-assembler
100// scratch V Registers.
102 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13,
103 d14, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27};
104
105// For the "WasmLiftoffFrameSetup" builtin.
106constexpr Register kLiftoffFrameSetupFunctionReg = x8;
107
108#elif V8_TARGET_ARCH_S390X
109
110constexpr RegList kLiftoffAssemblerGpCacheRegs = {r2, r3, r4, r5,
111 r6, r7, r8, cp};
112
114 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12};
115
116// For the "WasmLiftoffFrameSetup" builtin.
117constexpr Register kLiftoffFrameSetupFunctionReg = r7;
118
119#elif V8_TARGET_ARCH_PPC64
120
121constexpr RegList kLiftoffAssemblerGpCacheRegs = {r3, r4, r5, r6, r7, r8,
122 r9, r10, r11, r15, cp};
123
125 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12};
126
127// For the "WasmLiftoffFrameSetup" builtin.
128constexpr Register kLiftoffFrameSetupFunctionReg = r15;
129
130#elif V8_TARGET_ARCH_RISCV32 || V8_TARGET_ARCH_RISCV64
131// Any change of kLiftoffAssemblerGpCacheRegs also need to update
132// kPushedGpRegs in frame-constants-riscv.h
133constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5,
134 a6, a7, t0, t1, t2, s7};
135
136// Any change of kLiftoffAssemblerGpCacheRegs also need to update
137// kPushedFpRegs in frame-constants-riscv.h
138// ft0 don't be putted int kLiftoffAssemblerFpCacheRegs because v0 is a special
139// simd register and code of ft0 and v0 is same.
141 ft1, ft2, ft3, ft4, ft5, ft6, ft7, fa0, fa1, fa2,
142 fa3, fa4, fa5, fa6, fa7, ft8, ft9, ft10, ft11};
143
144// For the "WasmLiftoffFrameSetup" builtin.
145constexpr Register kLiftoffFrameSetupFunctionReg = t0;
146#else
147
149
152
153#endif
154
155static_assert(kLiftoffFrameSetupFunctionReg != kWasmImplicitArgRegister);
156static_assert(kLiftoffFrameSetupFunctionReg != kRootRegister);
157#ifdef V8_COMPRESS_POINTERS
158static_assert(kLiftoffFrameSetupFunctionReg != kPtrComprCageBaseRegister);
159#endif
160
161} // namespace wasm
162} // namespace internal
163} // namespace v8
164
165#endif // V8_WASM_BASELINE_LIFTOFF_ASSEMBLER_DEFS_H_
static constexpr RegListBase FromBits()
constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs
uint32_t WasmInterpreterRuntime int64_t r0
constexpr RegList kLiftoffAssemblerGpCacheRegs
constexpr Register kRootRegister
RegListBase< DoubleRegister > DoubleRegList
Definition reglist-arm.h:15
RegListBase< Register > RegList
Definition reglist-arm.h:14
constexpr Register kWasmImplicitArgRegister
constexpr Register r11
constexpr Register kPtrComprCageBaseRegister
constexpr Register cp
Definition c-api.cc:87