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v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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This is the complete list of members for v8::internal::AssemblerRISCVV, including all inherited members.
| BlockTrampolinePoolFor(int instructions)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| branch_offset_helper(Label *L, OffsetSize bits)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| ClearVectorunit()=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| emit(Instr x)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| emit(ShortInstr x)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| emit(uint64_t x)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| GenInstrALU_ri(uint8_t funct3, Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALU_rr(uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, FPURegister rs1, FPURegister rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, FPURegister rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd, FPURegister rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd, FPURegister rs1, FPURegister rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUW_rr(uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrB(uint8_t funct3, BaseOpcode opcode, Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrBranchCC_rri(uint8_t funct3, Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCA(uint8_t funct6, BaseOpcode opcode, Register rd, uint8_t funct, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCB(uint8_t funct3, BaseOpcode opcode, Register rs1, uint8_t uimm8) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCBA(uint8_t funct3, uint8_t funct2, BaseOpcode opcode, Register rs1, int8_t imm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCI(uint8_t funct3, BaseOpcode opcode, Register rd, int8_t imm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCIU(uint8_t funct3, BaseOpcode opcode, Register rd, uint8_t uimm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCIU(uint8_t funct3, BaseOpcode opcode, FPURegister rd, uint8_t uimm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCIW(uint8_t funct3, BaseOpcode opcode, Register rd, uint8_t uimm8) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCJ(uint8_t funct3, BaseOpcode opcode, uint16_t uint11) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCL(uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t uimm5) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCL(uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, uint8_t uimm5) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCR(uint8_t funct4, BaseOpcode opcode, Register rd, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCS(uint8_t funct3, BaseOpcode opcode, Register rs2, Register rs1, uint8_t uimm5) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCS(uint8_t funct3, BaseOpcode opcode, FPURegister rs2, Register rs1, uint8_t uimm5) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCSR_ii(uint8_t funct3, Register rd, ControlStatusReg csr, uint8_t rs1) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCSR_ir(uint8_t funct3, Register rd, ControlStatusReg csr, Register rs1) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCSS(uint8_t funct3, BaseOpcode opcode, FPURegister rs2, uint8_t uimm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCSS(uint8_t funct3, BaseOpcode opcode, Register rs2, uint8_t uimm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrI(uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrI(uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrIShift(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrIShiftW(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrJ(BaseOpcode opcode, Register rd, int32_t imm20) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrLoad_ri(uint8_t funct3, Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrLoadFP_ri(uint8_t funct3, FPURegister rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrPriv(uint8_t funct7, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, FPURegister rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, FPURegister rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, FPURegister rs1, FPURegister rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR4(uint8_t funct2, BaseOpcode opcode, Register rd, Register rs1, Register rs2, Register rs3, FPURoundingMode frm) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR4(uint8_t funct2, BaseOpcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2, FPURegister rs3, FPURoundingMode frm) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrRAtomic(uint8_t funct5, bool aq, bool rl, uint8_t funct3, Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrRFrm(uint8_t funct7, BaseOpcode opcode, Register rd, Register rs1, Register rs2, FPURoundingMode frm) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrS(uint8_t funct3, BaseOpcode opcode, Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrS(uint8_t funct3, BaseOpcode opcode, Register rs1, FPURegister rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrShift_ri(bool arithshift, uint8_t funct3, Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrShiftW_ri(bool arithshift, uint8_t funct3, Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrStore_rri(uint8_t funct3, Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrStoreFP_rri(uint8_t funct3, Register rs1, FPURegister rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrU(BaseOpcode opcode, Register rd, int32_t imm20) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrV(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(Register rd, Register rs1, uint32_t zimm) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, VRegister vs1, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, int8_t vs1, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Opcode opcode, Register rd, VRegister vs1, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Opcode opcode, FPURegister fd, VRegister vs1, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, Register rs1, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, FPURegister fs1, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Register rd, Register rs1, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, VRegister vd, int8_t simm5, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(BaseOpcode opcode, uint8_t width, VRegister vd, Register rs1, uint8_t umop, MaskType mask, uint8_t IsMop, bool IsMew, uint8_t Nf) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(BaseOpcode opcode, uint8_t width, VRegister vd, Register rs1, Register rs2, MaskType mask, uint8_t IsMop, bool IsMew, uint8_t Nf) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(BaseOpcode opcode, uint8_t width, VRegister vd, Register rs1, VRegister vs2, MaskType mask, uint8_t IsMop, bool IsMew, uint8_t Nf) | v8::internal::AssemblerRISCVV | protected |
| GenInstrV(uint8_t funct6, Opcode opcode, Register rd, uint8_t vs1, VRegister vs2, MaskType mask) | v8::internal::AssemblerRISCVV | protected |
| GenZimm(VSew vsew, Vlmul vlmul, TailAgnosticType tail=tu, MaskAgnosticType mask=mu) | v8::internal::AssemblerRISCVV | inlinestatic |
| kOffset11 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset12 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset13 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset20 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset21 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset32 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset9 enum value | v8::internal::AssemblerRiscvBase | protected |
| OffsetSize enum name | v8::internal::AssemblerRiscvBase | protected |
| SegInstr(vl) SegInstr(vs) SegInstr(vls) SegInstr(vss) SegInstr(vsx) SegInstr(vlx) void vmv_vv(VRegister vd | v8::internal::AssemblerRISCVV | |
| vadc_vi(VRegister vd, uint8_t imm5, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vadc_vv(VRegister vd, VRegister vs1, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vadc_vx(VRegister vd, Register rs1, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vcpop_m(Register rd, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vfabs_vv(VRegister dst, VRegister src, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | inline |
| vfirst_m(Register rd, VRegister vs2, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vfmerge_vf(VRegister vd, FPURegister fs1, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vfmv_fs(FPURegister fd, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vfmv_sf(VRegister vd, FPURegister fs) | v8::internal::AssemblerRISCVV | |
| vfmv_vf(VRegister vd, FPURegister fs1) | v8::internal::AssemblerRISCVV | |
| vfneg_vv(VRegister dst, VRegister src, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | inline |
| vid_v(VRegister vd, MaskType mask=Mask) | v8::internal::AssemblerRISCVV | |
| vl(VRegister vd, Register rs1, uint8_t lumop, VSew vsew, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vls(VRegister vd, Register rs1, Register rs2, VSew vsew, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vlx(VRegister vd, Register rs1, VRegister vs3, VSew vsew, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vmadc_vi(VRegister vd, uint8_t imm5, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vmadc_vv(VRegister vd, VRegister vs1, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vmadc_vx(VRegister vd, Register rs1, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vmerge_vi(VRegister vd, uint8_t imm5, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vmerge_vv(VRegister vd, VRegister vs1, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vmerge_vx(VRegister vd, Register rs1, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vmslt_vi(VRegister vd, VRegister vs1, int8_t imm5, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | inline |
| vmsltu_vi(VRegister vd, VRegister vs1, int8_t imm5, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | inline |
| vmv_sx(VRegister vd, Register rs1) | v8::internal::AssemblerRISCVV | |
| vmv_vi(VRegister vd, uint8_t simm5) | v8::internal::AssemblerRISCVV | |
| vmv_vx(VRegister vd, Register rs1) | v8::internal::AssemblerRISCVV | |
| vmv_xs(Register rd, VRegister vs2) | v8::internal::AssemblerRISCVV | |
| vneg_vv(VRegister dst, VRegister src, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | inline |
| vnot_vv(VRegister dst, VRegister src, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | inline |
| vredmax_vs(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vredmaxu_vs(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vredmin_vs(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vredminu_vs(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vs(VRegister vd, Register rs1, uint8_t sumop, VSew vsew, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vs1 | v8::internal::AssemblerRISCVV | |
| vsetivli(Register rd, uint8_t uimm, VSew vsew, Vlmul vlmul, TailAgnosticType tail=tu, MaskAgnosticType mask=mu) | v8::internal::AssemblerRISCVV | protected |
| vsetvl(VSew vsew, Vlmul vlmul, TailAgnosticType tail=tu, MaskAgnosticType mask=mu) | v8::internal::AssemblerRISCVV | inlineprotected |
| vsetvl(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVV | protected |
| vsetvli(Register rd, Register rs1, VSew vsew, Vlmul vlmul, TailAgnosticType tail=tu, MaskAgnosticType mask=mu) | v8::internal::AssemblerRISCVV | protected |
| vsetvlmax(Register rd, VSew vsew, Vlmul vlmul, TailAgnosticType tail=tu, MaskAgnosticType mask=mu) | v8::internal::AssemblerRISCVV | inlineprotected |
| vss(VRegister vd, Register rs1, Register rs2, VSew vsew, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vsu(VRegister vd, Register rs1, VRegister vs3, VSew vsew, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vsx(VRegister vd, Register rs1, VRegister vs3, VSew vsew, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV | |
| vwaddu_wx(VRegister vd, VRegister vs2, Register rs1, MaskType mask=NoMask) | v8::internal::AssemblerRISCVV |
1.12.0