v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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code-generator-arm64.cc File Reference
#include "src/codegen/arm64/assembler-arm64-inl.h"
#include "src/codegen/arm64/constants-arm64.h"
#include "src/codegen/arm64/macro-assembler-arm64-inl.h"
#include "src/codegen/interface-descriptors-inl.h"
#include "src/codegen/machine-type.h"
#include "src/codegen/optimized-compilation-info.h"
#include "src/compiler/backend/code-generator-impl.h"
#include "src/compiler/backend/code-generator.h"
#include "src/compiler/backend/gap-resolver.h"
#include "src/compiler/backend/instruction-codes.h"
#include "src/compiler/node-matchers.h"
#include "src/compiler/osr.h"
#include "src/execution/frame-constants.h"
#include "src/heap/mutable-page-metadata.h"
Include dependency graph for code-generator-arm64.cc:

Go to the source code of this file.

Classes

class  v8::internal::compiler::Arm64OperandConverter
 

Namespaces

namespace  v8
 
namespace  v8::internal
 
namespace  v8::internal::compiler
 

Macros

#define __   masm()->
 
#define ASSEMBLE_SHIFT(asm_instr, width)
 
#define ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr, reg)
 
#define ASSEMBLE_ATOMIC_STORE_INTEGER(asm_instr, reg)
 
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(suffix, reg)
 
#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(suffix, ext, reg)
 
#define ASSEMBLE_ATOMIC_SUB(suffix, reg)
 
#define ASSEMBLE_ATOMIC_AND(suffix, reg)
 
#define ASSEMBLE_ATOMIC_BINOP(suffix, bin_instr, lse_instr, reg)
 
#define ASSEMBLE_IEEE754_BINOP(name)
 
#define ASSEMBLE_IEEE754_UNOP(name)
 
#define ASSEMBLE_SIMD_SHIFT_LEFT(asm_imm, width, format, asm_shl, gp)
 
#define ASSEMBLE_SIMD_SHIFT_RIGHT(asm_imm, width, format, asm_shl, gp)
 
#define ATOMIC_BINOP_CASE(op, inst, lse_instr)
 

Functions

int32_t v8::internal::compiler::GetLaneMask (int32_t lane_count)
 
void v8::internal::compiler::Shuffle1Helper (MacroAssembler *masm, Arm64OperandConverter i, VectorFormat f)
 
void v8::internal::compiler::Shuffle2Helper (MacroAssembler *masm, Arm64OperandConverter i, VectorFormat f)
 
void v8::internal::compiler::Shuffle4Helper (MacroAssembler *masm, Arm64OperandConverter i, VectorFormat f)
 
StatusFlags v8::internal::compiler::ConditionToDefaultFlags (Condition condition)
 
void v8::internal::compiler::AssembleConditionalCompareChain (Instruction *instr, int64_t num_ccmps, size_t ccmp_base_index, CodeGenerator *gen)
 

Macro Definition Documentation

◆ __

#define __   masm()->

Definition at line 29 of file code-generator-arm64.cc.

◆ ASSEMBLE_ATOMIC_AND

#define ASSEMBLE_ATOMIC_AND ( suffix,
reg )
Value:
do { \
__ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
if (CpuFeatures::IsSupported(LSE)) { \
CpuFeatureScope scope(masm(), LSE); \
UseScratchRegisterScope temps(masm()); \
Register scratch = temps.AcquireSameSizeAs(i.Input##reg(2)); \
__ Mvn(scratch, i.Input##reg(2)); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ Ldclral##suffix(scratch, i.Output##reg(), \
MemOperand(i.TempRegister(0))); \
} else { \
Label binop; \
__ Bind(&binop); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ ldaxr##suffix(i.Output##reg(), i.TempRegister(0)); \
__ And(i.Temp##reg(1), i.Output##reg(), Operand(i.Input##reg(2))); \
__ stlxr##suffix(i.TempRegister32(2), i.Temp##reg(1), \
i.TempRegister(0)); \
__ Cbnz(i.TempRegister32(2), &binop); \
} \
} while (0)
__
#define __
Definition code-generator-arm64.cc:29
instr
Instruction * instr
Definition jump-threading.cc:63
reg
LiftoffRegister reg
Definition liftoff-compiler.cc:512
pc_offset
int pc_offset
Definition liftoff-compiler.cc:9470

Definition at line 594 of file code-generator-arm64.cc.

◆ ASSEMBLE_ATOMIC_BINOP

#define ASSEMBLE_ATOMIC_BINOP ( suffix,
bin_instr,
lse_instr,
reg )
Value:
do { \
__ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
if (CpuFeatures::IsSupported(LSE)) { \
CpuFeatureScope scope(masm(), LSE); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ lse_instr##suffix(i.Input##reg(2), i.Output##reg(), \
MemOperand(i.TempRegister(0))); \
} else { \
Label binop; \
__ Bind(&binop); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ ldaxr##suffix(i.Output##reg(), i.TempRegister(0)); \
__ bin_instr(i.Temp##reg(1), i.Output##reg(), Operand(i.Input##reg(2))); \
__ stlxr##suffix(i.TempRegister32(2), i.Temp##reg(1), \
i.TempRegister(0)); \
__ Cbnz(i.TempRegister32(2), &binop); \
} \
} while (0)

Definition at line 617 of file code-generator-arm64.cc.

◆ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER

#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER ( suffix,
ext,
reg )
Value:
do { \
__ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
if (CpuFeatures::IsSupported(LSE)) { \
DCHECK_EQ(i.OutputRegister(), i.InputRegister(2)); \
CpuFeatureScope scope(masm(), LSE); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ Casal##suffix(i.Output##reg(), i.Input##reg(3), \
MemOperand(i.TempRegister(0))); \
} else { \
Label compareExchange; \
Label exit; \
__ Bind(&compareExchange); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ ldaxr##suffix(i.Output##reg(), i.TempRegister(0)); \
__ Cmp(i.Output##reg(), Operand(i.Input##reg(2), ext)); \
__ B(ne, &exit); \
__ stlxr##suffix(i.TempRegister32(1), i.Input##reg(3), \
i.TempRegister(0)); \
__ Cbnz(i.TempRegister32(1), &compareExchange); \
__ Bind(&exit); \
} \
} while (0)

Definition at line 547 of file code-generator-arm64.cc.

◆ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER

#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER ( suffix,
reg )
Value:
do { \
__ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
if (CpuFeatures::IsSupported(LSE)) { \
CpuFeatureScope scope(masm(), LSE); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ Swpal##suffix(i.Input##reg(2), i.Output##reg(), \
MemOperand(i.TempRegister(0))); \
} else { \
Label exchange; \
__ Bind(&exchange); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ ldaxr##suffix(i.Output##reg(), i.TempRegister(0)); \
__ stlxr##suffix(i.TempRegister32(1), i.Input##reg(2), \
i.TempRegister(0)); \
__ Cbnz(i.TempRegister32(1), &exchange); \
} \
} while (0)

Definition at line 528 of file code-generator-arm64.cc.

◆ ASSEMBLE_ATOMIC_LOAD_INTEGER

#define ASSEMBLE_ATOMIC_LOAD_INTEGER ( asm_instr,
reg )
Value:
do { \
__ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ asm_instr(i.Output##reg(), i.TempRegister(0)); \
} while (0)

Definition at line 514 of file code-generator-arm64.cc.

◆ ASSEMBLE_ATOMIC_STORE_INTEGER

#define ASSEMBLE_ATOMIC_STORE_INTEGER ( asm_instr,
reg )
Value:
do { \
__ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ asm_instr(i.Input##reg(2), i.TempRegister(0)); \
} while (0)

Definition at line 521 of file code-generator-arm64.cc.

◆ ASSEMBLE_ATOMIC_SUB

#define ASSEMBLE_ATOMIC_SUB ( suffix,
reg )
Value:
do { \
__ Add(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
if (CpuFeatures::IsSupported(LSE)) { \
CpuFeatureScope scope(masm(), LSE); \
UseScratchRegisterScope temps(masm()); \
Register scratch = temps.AcquireSameSizeAs(i.Input##reg(2)); \
__ Neg(scratch, i.Input##reg(2)); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ Ldaddal##suffix(scratch, i.Output##reg(), \
MemOperand(i.TempRegister(0))); \
} else { \
Label binop; \
__ Bind(&binop); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ ldaxr##suffix(i.Output##reg(), i.TempRegister(0)); \
__ Sub(i.Temp##reg(1), i.Output##reg(), Operand(i.Input##reg(2))); \
__ stlxr##suffix(i.TempRegister32(2), i.Temp##reg(1), \
i.TempRegister(0)); \
__ Cbnz(i.TempRegister32(2), &binop); \
} \
} while (0)

Definition at line 571 of file code-generator-arm64.cc.

◆ ASSEMBLE_IEEE754_BINOP

#define ASSEMBLE_IEEE754_BINOP ( name)
Value:
do { \
FrameScope scope(masm(), StackFrame::MANUAL); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 2); \
} while (0)

Definition at line 637 of file code-generator-arm64.cc.

◆ ASSEMBLE_IEEE754_UNOP

#define ASSEMBLE_IEEE754_UNOP ( name)
Value:
do { \
FrameScope scope(masm(), StackFrame::MANUAL); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 1); \
} while (0)

Definition at line 643 of file code-generator-arm64.cc.

◆ ASSEMBLE_SHIFT

#define ASSEMBLE_SHIFT ( asm_instr,
width )
Value:
do { \
if (instr->InputAt(1)->IsRegister()) { \
__ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0), \
i.InputRegister##width(1)); \
} else { \
uint32_t imm = \
static_cast<uint32_t>(i.InputOperand##width(1).ImmediateValue()); \
__ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0), \
imm % (width)); \
} \
} while (0)

Definition at line 501 of file code-generator-arm64.cc.

◆ ASSEMBLE_SIMD_SHIFT_LEFT

#define ASSEMBLE_SIMD_SHIFT_LEFT ( asm_imm,
width,
format,
asm_shl,
gp )
Value:
do { \
if (instr->InputAt(1)->IsImmediate()) { \
__ asm_imm(i.OutputSimd128Register().format(), \
i.InputSimd128Register(0).format(), i.InputInt##width(1)); \
} else { \
UseScratchRegisterScope temps(masm()); \
VRegister tmp = temps.AcquireQ(); \
Register shift = temps.Acquire##gp(); \
constexpr int mask = (1 << width) - 1; \
__ And(shift, i.InputRegister32(1), mask); \
__ Dup(tmp.format(), shift); \
__ asm_shl(i.OutputSimd128Register().format(), \
i.InputSimd128Register(0).format(), tmp.format()); \
} \
} while (0)
mask
uint32_t const mask
Definition machine-operator-reducer.cc:2278

Definition at line 652 of file code-generator-arm64.cc.

◆ ASSEMBLE_SIMD_SHIFT_RIGHT

#define ASSEMBLE_SIMD_SHIFT_RIGHT ( asm_imm,
width,
format,
asm_shl,
gp )
Value:
do { \
if (instr->InputAt(1)->IsImmediate()) { \
__ asm_imm(i.OutputSimd128Register().format(), \
i.InputSimd128Register(0).format(), i.InputInt##width(1)); \
} else { \
UseScratchRegisterScope temps(masm()); \
VRegister tmp = temps.AcquireQ(); \
Register shift = temps.Acquire##gp(); \
constexpr int mask = (1 << width) - 1; \
__ And(shift, i.InputRegister32(1), mask); \
__ Dup(tmp.format(), shift); \
__ Neg(tmp.format(), tmp.format()); \
__ asm_shl(i.OutputSimd128Register().format(), \
i.InputSimd128Register(0).format(), tmp.format()); \
} \
} while (0)

Definition at line 672 of file code-generator-arm64.cc.

◆ ATOMIC_BINOP_CASE

#define ATOMIC_BINOP_CASE ( op,
inst,
lse_instr )
Value:
case kAtomic##op##Int8: \
ASSEMBLE_ATOMIC_BINOP(b, inst, lse_instr, Register32); \
__ Sxtb(i.OutputRegister(0), i.OutputRegister(0)); \
break; \
case kAtomic##op##Uint8: \
ASSEMBLE_ATOMIC_BINOP(b, inst, lse_instr, Register32); \
break; \
case kAtomic##op##Int16: \
ASSEMBLE_ATOMIC_BINOP(h, inst, lse_instr, Register32); \
__ Sxth(i.OutputRegister(0), i.OutputRegister(0)); \
break; \
case kAtomic##op##Uint16: \
ASSEMBLE_ATOMIC_BINOP(h, inst, lse_instr, Register32); \
break; \
case kAtomic##op##Word32: \
ASSEMBLE_ATOMIC_BINOP(, inst, lse_instr, Register32); \
break; \
case kArm64Word64Atomic##op##Uint64: \
ASSEMBLE_ATOMIC_BINOP(, inst, lse_instr, Register); \
break;

Variable Documentation

◆ indirect_pointer_tag_

IndirectPointerTag indirect_pointer_tag_
private

Definition at line 383 of file code-generator-arm64.cc.

◆ mode_

RecordWriteMode const mode_
private

Definition at line 376 of file code-generator-arm64.cc.

◆ must_save_lr_

bool must_save_lr_
private

Definition at line 380 of file code-generator-arm64.cc.

◆ object_

Register const object_
private

Definition at line 373 of file code-generator-arm64.cc.

◆ offset_

Operand const offset_
private

Definition at line 374 of file code-generator-arm64.cc.

◆ unwinding_info_writer_

UnwindingInfoWriter* const unwinding_info_writer_
private

Definition at line 381 of file code-generator-arm64.cc.

◆ value_

Register const value_
private

Definition at line 375 of file code-generator-arm64.cc.

◆ zone_

Zone* zone_
private

Definition at line 382 of file code-generator-arm64.cc.