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V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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code-generator-arm.cc File Reference
#include "src/base/numbers/double.h"
#include "src/codegen/arm/assembler-arm.h"
#include "src/codegen/arm/constants-arm.h"
#include "src/codegen/arm/register-arm.h"
#include "src/codegen/assembler-inl.h"
#include "src/codegen/interface-descriptors-inl.h"
#include "src/codegen/machine-type.h"
#include "src/codegen/macro-assembler.h"
#include "src/codegen/optimized-compilation-info.h"
#include "src/common/globals.h"
#include "src/compiler/backend/code-generator-impl.h"
#include "src/compiler/backend/code-generator.h"
#include "src/compiler/backend/gap-resolver.h"
#include "src/compiler/backend/instruction-codes.h"
#include "src/compiler/node-matchers.h"
#include "src/compiler/osr.h"
#include "src/heap/mutable-page-metadata.h"
#include "src/utils/boxed-float.h"
Include dependency graph for code-generator-arm.cc:

Go to the source code of this file.

Classes

class  v8::internal::compiler::ArmOperandConverter
 

Namespaces

namespace  v8
 
namespace  v8::internal
 
namespace  v8::internal::compiler
 

Macros

#define __   masm()->
 
#define ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr)
 
#define ASSEMBLE_ATOMIC_STORE_INTEGER(asm_instr, order)
 
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(load_instr, store_instr)
 
#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(load_instr, store_instr, cmp_reg)
 
#define ASSEMBLE_ATOMIC_BINOP(load_instr, store_instr, bin_instr)
 
#define ASSEMBLE_ATOMIC64_ARITH_BINOP(instr1, instr2)
 
#define ASSEMBLE_ATOMIC64_LOGIC_BINOP(instr)
 
#define ASSEMBLE_IEEE754_BINOP(name)
 
#define ASSEMBLE_IEEE754_UNOP(name)
 
#define ASSEMBLE_NEON_NARROWING_OP(dt, sdt)
 
#define ASSEMBLE_F64X2_ARITHMETIC_BINOP(op)
 
#define ASSEMBLE_SIMD_SHIFT_LEFT(asm_imm, width, sz, dt)
 
#define ASSEMBLE_SIMD_SHIFT_RIGHT(asm_imm, width, sz, dt)
 
#define S_FROM_Q(reg, lane)
 
#define S_FROM_Q(reg, lane)
 
#define ATOMIC_BINOP_CASE(op, inst)
 
#define ATOMIC_ARITH_BINOP_CASE(op, instr1, instr2)
 
#define ATOMIC_LOGIC_BINOP_CASE(op, instr1)
 

Macro Definition Documentation

◆ __

#define __   masm()->

Definition at line 33 of file code-generator-arm.cc.

◆ ASSEMBLE_ATOMIC64_ARITH_BINOP

#define ASSEMBLE_ATOMIC64_ARITH_BINOP ( instr1,
instr2 )
Value:
do { \
Label binop; \
__ add(i.TempRegister(0), i.InputRegister(2), i.InputRegister(3)); \
__ dmb(ISH); \
__ bind(&binop); \
__ ldrexd(r2, r3, i.TempRegister(0)); \
__ instr1(i.TempRegister(1), r2, i.InputRegister(0), SetCC); \
__ instr2(i.TempRegister(2), r3, Operand(i.InputRegister(1))); \
DCHECK_EQ(LeaveCC, i.OutputSBit()); \
__ strexd(i.TempRegister(3), i.TempRegister(1), i.TempRegister(2), \
i.TempRegister(0)); \
__ teq(i.TempRegister(3), Operand(0)); \
__ b(ne, &binop); \
__ dmb(ISH); \
} while (0)
__
#define __
Definition code-generator-arm.cc:33

Definition at line 378 of file code-generator-arm.cc.

◆ ASSEMBLE_ATOMIC64_LOGIC_BINOP

#define ASSEMBLE_ATOMIC64_LOGIC_BINOP ( instr)
Value:
do { \
Label binop; \
__ add(i.TempRegister(0), i.InputRegister(2), i.InputRegister(3)); \
__ dmb(ISH); \
__ bind(&binop); \
__ ldrexd(r2, r3, i.TempRegister(0)); \
__ instr(i.TempRegister(1), r2, Operand(i.InputRegister(0))); \
__ instr(i.TempRegister(2), r3, Operand(i.InputRegister(1))); \
__ strexd(i.TempRegister(3), i.TempRegister(1), i.TempRegister(2), \
i.TempRegister(0)); \
__ teq(i.TempRegister(3), Operand(0)); \
__ b(ne, &binop); \
__ dmb(ISH); \
} while (0)
instr
Instruction * instr
Definition jump-threading.cc:63

Definition at line 395 of file code-generator-arm.cc.

◆ ASSEMBLE_ATOMIC_BINOP

#define ASSEMBLE_ATOMIC_BINOP ( load_instr,
store_instr,
bin_instr )
Value:
do { \
Label binop; \
__ add(i.TempRegister(1), i.InputRegister(0), i.InputRegister(1)); \
__ dmb(ISH); \
__ bind(&binop); \
__ load_instr(i.OutputRegister(0), i.TempRegister(1)); \
__ bin_instr(i.TempRegister(0), i.OutputRegister(0), \
Operand(i.InputRegister(2))); \
__ store_instr(i.TempRegister(2), i.TempRegister(0), i.TempRegister(1)); \
__ teq(i.TempRegister(2), Operand(0)); \
__ b(ne, &binop); \
__ dmb(ISH); \
} while (0)

Definition at line 363 of file code-generator-arm.cc.

◆ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER

#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER ( load_instr,
store_instr,
cmp_reg )
Value:
do { \
Label compareExchange; \
Label exit; \
__ dmb(ISH); \
__ bind(&compareExchange); \
__ load_instr(i.OutputRegister(0), i.TempRegister(1)); \
__ teq(cmp_reg, Operand(i.OutputRegister(0))); \
__ b(ne, &exit); \
__ store_instr(i.TempRegister(0), i.InputRegister(3), i.TempRegister(1)); \
__ teq(i.TempRegister(0), Operand(0)); \
__ b(ne, &compareExchange); \
__ bind(&exit); \
__ dmb(ISH); \
} while (0)

Definition at line 346 of file code-generator-arm.cc.

◆ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER

#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER ( load_instr,
store_instr )
Value:
do { \
Label exchange; \
__ add(i.TempRegister(1), i.InputRegister(0), i.InputRegister(1)); \
__ dmb(ISH); \
__ bind(&exchange); \
__ load_instr(i.OutputRegister(0), i.TempRegister(1)); \
__ store_instr(i.TempRegister(0), i.InputRegister(2), i.TempRegister(1)); \
__ teq(i.TempRegister(0), Operand(0)); \
__ b(ne, &exchange); \
__ dmb(ISH); \
} while (0)

Definition at line 333 of file code-generator-arm.cc.

◆ ASSEMBLE_ATOMIC_LOAD_INTEGER

#define ASSEMBLE_ATOMIC_LOAD_INTEGER ( asm_instr)
Value:
do { \
__ asm_instr(i.OutputRegister(), \
MemOperand(i.InputRegister(0), i.InputRegister(1))); \
__ dmb(ISH); \
} while (0)

Definition at line 319 of file code-generator-arm.cc.

◆ ASSEMBLE_ATOMIC_STORE_INTEGER

#define ASSEMBLE_ATOMIC_STORE_INTEGER ( asm_instr,
order )
Value:
do { \
__ dmb(ISH); \
__ asm_instr(i.InputRegister(0), i.InputOffset(1)); \
if (order == AtomicMemoryOrder::kSeqCst) __ dmb(ISH); \
} while (0)

Definition at line 326 of file code-generator-arm.cc.

◆ ASSEMBLE_F64X2_ARITHMETIC_BINOP

#define ASSEMBLE_F64X2_ARITHMETIC_BINOP ( op)
Value:
do { \
__ op(i.OutputSimd128Register().low(), i.InputSimd128Register(0).low(), \
i.InputSimd128Register(1).low()); \
__ op(i.OutputSimd128Register().high(), i.InputSimd128Register(0).high(), \
i.InputSimd128Register(1).high()); \
} while (0)

Definition at line 455 of file code-generator-arm.cc.

◆ ASSEMBLE_IEEE754_BINOP

#define ASSEMBLE_IEEE754_BINOP ( name)
Value:
do { \
/* TODO(bmeurer): We should really get rid of this special instruction, */ \
/* and generate a CallAddress instruction instead. */ \
FrameScope scope(masm(), StackFrame::MANUAL); \
__ PrepareCallCFunction(0, 2); \
__ MovToFloatParameters(i.InputDoubleRegister(0), \
i.InputDoubleRegister(1)); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 2); \
/* Move the result in the double result register. */ \
__ MovFromFloatResult(i.OutputDoubleRegister()); \
DCHECK_EQ(LeaveCC, i.OutputSBit()); \
} while (0)

Definition at line 411 of file code-generator-arm.cc.

◆ ASSEMBLE_IEEE754_UNOP

#define ASSEMBLE_IEEE754_UNOP ( name)
Value:
do { \
/* TODO(bmeurer): We should really get rid of this special instruction, */ \
/* and generate a CallAddress instruction instead. */ \
FrameScope scope(masm(), StackFrame::MANUAL); \
__ PrepareCallCFunction(0, 1); \
__ MovToFloatParameter(i.InputDoubleRegister(0)); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 1); \
/* Move the result in the double result register. */ \
__ MovFromFloatResult(i.OutputDoubleRegister()); \
DCHECK_EQ(LeaveCC, i.OutputSBit()); \
} while (0)

Definition at line 425 of file code-generator-arm.cc.

◆ ASSEMBLE_NEON_NARROWING_OP

#define ASSEMBLE_NEON_NARROWING_OP ( dt,
sdt )
Value:
do { \
Simd128Register dst = i.OutputSimd128Register(), \
src0 = i.InputSimd128Register(0), \
src1 = i.InputSimd128Register(1); \
if (dst == src0 && dst == src1) { \
__ vqmovn(dt, sdt, dst.low(), src0); \
__ vmov(dst.high(), dst.low()); \
} else if (dst == src0) { \
__ vqmovn(dt, sdt, dst.low(), src0); \
__ vqmovn(dt, sdt, dst.high(), src1); \
} else { \
__ vqmovn(dt, sdt, dst.high(), src1); \
__ vqmovn(dt, sdt, dst.low(), src0); \
} \
} while (0)

Definition at line 438 of file code-generator-arm.cc.

◆ ASSEMBLE_SIMD_SHIFT_LEFT

#define ASSEMBLE_SIMD_SHIFT_LEFT ( asm_imm,
width,
sz,
dt )
Value:
do { \
QwNeonRegister dst = i.OutputSimd128Register(); \
QwNeonRegister src = i.InputSimd128Register(0); \
if (instr->InputAt(1)->IsImmediate()) { \
__ asm_imm(dt, dst, src, i.InputInt##width(1)); \
} else { \
UseScratchRegisterScope temps(masm()); \
Simd128Register tmp = temps.AcquireQ(); \
Register shift = temps.Acquire(); \
constexpr int mask = (1 << width) - 1; \
__ and_(shift, i.InputRegister(1), Operand(mask)); \
__ vdup(sz, tmp, shift); \
__ vshl(dt, dst, src, tmp); \
} \
} while (0)
mask
uint32_t const mask
Definition machine-operator-reducer.cc:2278

Definition at line 466 of file code-generator-arm.cc.

◆ ASSEMBLE_SIMD_SHIFT_RIGHT

#define ASSEMBLE_SIMD_SHIFT_RIGHT ( asm_imm,
width,
sz,
dt )
Value:
do { \
QwNeonRegister dst = i.OutputSimd128Register(); \
QwNeonRegister src = i.InputSimd128Register(0); \
if (instr->InputAt(1)->IsImmediate()) { \
__ asm_imm(dt, dst, src, i.InputInt##width(1)); \
} else { \
UseScratchRegisterScope temps(masm()); \
Simd128Register tmp = temps.AcquireQ(); \
Register shift = temps.Acquire(); \
constexpr int mask = (1 << width) - 1; \
__ and_(shift, i.InputRegister(1), Operand(mask)); \
__ vdup(sz, tmp, shift); \
__ vneg(sz, tmp, tmp); \
__ vshl(dt, dst, src, tmp); \
} \
} while (0)

Definition at line 486 of file code-generator-arm.cc.

◆ ATOMIC_ARITH_BINOP_CASE

#define ATOMIC_ARITH_BINOP_CASE ( op,
instr1,
instr2 )
Value:
case kArmWord32AtomicPair##op: { \
DCHECK(VerifyOutputOfAtomicPairInstr(&i, instr, r2, r3)); \
ASSEMBLE_ATOMIC64_ARITH_BINOP(instr1, instr2); \
break; \
}

◆ ATOMIC_BINOP_CASE

#define ATOMIC_BINOP_CASE ( op,
inst )
Value:
case kAtomic##op##Int8: \
ASSEMBLE_ATOMIC_BINOP(ldrexb, strexb, inst); \
__ sxtb(i.OutputRegister(0), i.OutputRegister(0)); \
break; \
case kAtomic##op##Uint8: \
ASSEMBLE_ATOMIC_BINOP(ldrexb, strexb, inst); \
break; \
case kAtomic##op##Int16: \
ASSEMBLE_ATOMIC_BINOP(ldrexh, strexh, inst); \
__ sxth(i.OutputRegister(0), i.OutputRegister(0)); \
break; \
case kAtomic##op##Uint16: \
ASSEMBLE_ATOMIC_BINOP(ldrexh, strexh, inst); \
break; \
case kAtomic##op##Word32: \
ASSEMBLE_ATOMIC_BINOP(ldrex, strex, inst); \
break;

◆ ATOMIC_LOGIC_BINOP_CASE

#define ATOMIC_LOGIC_BINOP_CASE ( op,
instr1 )
Value:
case kArmWord32AtomicPair##op: { \
DCHECK(VerifyOutputOfAtomicPairInstr(&i, instr, r2, r3)); \
ASSEMBLE_ATOMIC64_LOGIC_BINOP(instr1); \
break; \
}

◆ S_FROM_Q [1/2]

#define S_FROM_Q ( reg,
lane )
Value:
SwVfpRegister::from_code(reg.code() * 4 + lane)
reg
LiftoffRegister reg
Definition liftoff-compiler.cc:512

◆ S_FROM_Q [2/2]

#define S_FROM_Q ( reg,
lane )
Value:
SwVfpRegister::from_code(reg.code() * 4 + lane)

Variable Documentation

◆ left_

T const left_
private

Definition at line 243 of file code-generator-arm.cc.

◆ mode_

RecordWriteMode const mode_
private

Definition at line 224 of file code-generator-arm.cc.

◆ must_save_lr_

bool must_save_lr_
private

Definition at line 228 of file code-generator-arm.cc.

◆ object_

Register const object_
private

Definition at line 221 of file code-generator-arm.cc.

◆ offset_

Operand const offset_
private

Definition at line 222 of file code-generator-arm.cc.

◆ result_

T const result_
private

Definition at line 242 of file code-generator-arm.cc.

◆ right_

T const right_
private

Definition at line 244 of file code-generator-arm.cc.

◆ unwinding_info_writer_

UnwindingInfoWriter* const unwinding_info_writer_
private

Definition at line 229 of file code-generator-arm.cc.

◆ value_

Register const value_
private

Definition at line 223 of file code-generator-arm.cc.

◆ zone_

Zone* zone_
private

Definition at line 230 of file code-generator-arm.cc.