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code-generator-ppc.cc File Reference
#include "src/base/numbers/double.h"
#include "src/codegen/assembler-inl.h"
#include "src/codegen/callable.h"
#include "src/codegen/interface-descriptors-inl.h"
#include "src/codegen/macro-assembler.h"
#include "src/codegen/optimized-compilation-info.h"
#include "src/compiler/backend/code-generator-impl.h"
#include "src/compiler/backend/code-generator.h"
#include "src/compiler/backend/gap-resolver.h"
#include "src/compiler/node-matchers.h"
#include "src/compiler/osr.h"
#include "src/heap/mutable-page-metadata.h"
Include dependency graph for code-generator-ppc.cc:

Go to the source code of this file.

Classes

class  v8::internal::compiler::PPCOperandConverter
 

Namespaces

namespace  v8
 
namespace  v8::internal
 
namespace  v8::internal::compiler
 

Macros

#define __   masm()->
 
#define kScratchReg   r11
 
#define ASSEMBLE_FLOAT_UNOP_RC(asm_instr, round)
 
#define ASSEMBLE_FLOAT_BINOP_RC(asm_instr, round)
 
#define ASSEMBLE_BINOP(asm_instr_reg, asm_instr_imm)
 
#define ASSEMBLE_BINOP_RC(asm_instr_reg, asm_instr_imm)
 
#define ASSEMBLE_BINOP_INT_RC(asm_instr_reg, asm_instr_imm)
 
#define ASSEMBLE_ADD_WITH_OVERFLOW()
 
#define ASSEMBLE_SUB_WITH_OVERFLOW()
 
#define ASSEMBLE_ADD_WITH_OVERFLOW32()
 
#define ASSEMBLE_SUB_WITH_OVERFLOW32()
 
#define ASSEMBLE_COMPARE(cmp_instr, cmpl_instr)
 
#define ASSEMBLE_FLOAT_COMPARE(cmp_instr)
 
#define ASSEMBLE_MODULO(div_instr, mul_instr)
 
#define ASSEMBLE_FLOAT_MODULO()
 
#define ASSEMBLE_IEEE754_UNOP(name)
 
#define ASSEMBLE_IEEE754_BINOP(name)
 
#define ASSEMBLE_LOAD_FLOAT(asm_instr, asm_instrp, asm_instrx)
 
#define ASSEMBLE_LOAD_INTEGER(asm_instr, asm_instrp, asm_instrx, must_be_aligned)
 
#define ASSEMBLE_LOAD_INTEGER_RR(asm_instr)
 
#define ASSEMBLE_STORE_FLOAT(asm_instr, asm_instrp, asm_instrx)
 
#define ASSEMBLE_STORE_INTEGER(asm_instr, asm_instrp, asm_instrx, must_be_aligned)
 
#define ASSEMBLE_STORE_INTEGER_RR(asm_instr)
 
#define CleanUInt32(x)
 
#define MAYBE_REVERSE_IF_WASM(dst, src, op, scratch, reset)
 
#define ASSEMBLE_ATOMIC_EXCHANGE(_type, reverse_op)
 
#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE(_type, reverse_op)
 
#define ASSEMBLE_ATOMIC_BINOP_BYTE(bin_inst, _type)
 
#define ASSEMBLE_ATOMIC_BINOP(bin_inst, _type, reverse_op, scratch)
 
#define DOUBLE_TO_INT32(op)
 
#define ATOMIC_BINOP_CASE(op, inst)
 
#define SIMD_BINOP_LIST(V)
 
#define EMIT_SIMD_BINOP(name)
 
#define SIMD_BINOP_WITH_SCRATCH_LIST(V)
 
#define EMIT_SIMD_BINOP_WITH_SCRATCH(name)
 
#define SIMD_SHIFT_LIST(V)
 
#define EMIT_SIMD_SHIFT(name)
 
#define SIMD_UNOP_LIST(V)
 
#define EMIT_SIMD_UNOP(name)
 
#define SIMD_UNOP_WITH_SCRATCH_LIST(V)
 
#define EMIT_SIMD_UNOP_WITH_SCRATCH(name)
 
#define SIMD_ALL_TRUE_LIST(V)
 
#define EMIT_SIMD_ALL_TRUE(name)
 
#define SIMD_QFM_LIST(V)
 
#define EMIT_SIMD_QFM(name)
 
#define SIMD_EXT_ADD_PAIRWISE_LIST(V)
 
#define EMIT_SIMD_EXT_ADD_PAIRWISE(name)
 
#define SIMD_LOAD_LANE_LIST(V)
 
#define EMIT_SIMD_LOAD_LANE(name, op)
 
#define SIMD_STORE_LANE_LIST(V)
 
#define EMIT_SIMD_STORE_LANE(name, op)
 
#define SIMD_LOAD_SPLAT(V)
 
#define EMIT_SIMD_LOAD_SPLAT(name, op)
 
#define PREP_LOAD_EXTEND()
 

Functions

static bool v8::internal::compiler::HasRegisterInput (Instruction *instr, size_t index)
 

Macro Definition Documentation

◆ __

#define __   masm()->

Definition at line 27 of file code-generator-ppc.cc.

◆ ASSEMBLE_ADD_WITH_OVERFLOW

#define ASSEMBLE_ADD_WITH_OVERFLOW ( )
Value:
do { \
if (HasRegisterInput(instr, 1)) { \
__ AddAndCheckForOverflow(i.OutputRegister(), i.InputRegister(0), \
i.InputRegister(1), kScratchReg, r0); \
} else { \
__ AddAndCheckForOverflow(i.OutputRegister(), i.InputRegister(0), \
i.InputInt32(1), kScratchReg, r0); \
} \
} while (0)
__
#define __
Definition code-generator-ppc.cc:27
kScratchReg
#define kScratchReg
Definition code-generator-ppc.cc:29
instr
Instruction * instr
Definition jump-threading.cc:63

Definition at line 358 of file code-generator-ppc.cc.

◆ ASSEMBLE_ADD_WITH_OVERFLOW32

#define ASSEMBLE_ADD_WITH_OVERFLOW32 ( )
Value:
do { \
ASSEMBLE_ADD_WITH_OVERFLOW(); \
__ extsw(kScratchReg, kScratchReg, SetRC); \
} while (0)

Definition at line 380 of file code-generator-ppc.cc.

◆ ASSEMBLE_ATOMIC_BINOP

#define ASSEMBLE_ATOMIC_BINOP ( bin_inst,
_type,
reverse_op,
scratch )

Definition at line 651 of file code-generator-ppc.cc.

◆ ASSEMBLE_ATOMIC_BINOP_BYTE

#define ASSEMBLE_ATOMIC_BINOP_BYTE ( bin_inst,
_type )
Value:
do { \
auto bin_op = [&](Register dst, Register lhs, Register rhs) { \
if (std::is_signed<_type>::value) { \
__ extsb(dst, lhs); \
__ bin_inst(dst, dst, rhs); \
} else { \
__ bin_inst(dst, lhs, rhs); \
} \
}; \
MemOperand dst_operand = \
MemOperand(i.InputRegister(0), i.InputRegister(1)); \
__ AtomicOps<_type>(dst_operand, i.InputRegister(2), i.OutputRegister(), \
kScratchReg, bin_op); \
break; \
} while (false)

Definition at line 634 of file code-generator-ppc.cc.

◆ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE

#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE ( _type,
reverse_op )
Value:
do { \
Register expected_val = i.InputRegister(2); \
Register new_val = i.InputRegister(3); \
Register dst = i.OutputRegister(); \
MAYBE_REVERSE_IF_WASM(ip, expected_val, reverse_op, kScratchReg, true); \
MAYBE_REVERSE_IF_WASM(r0, new_val, reverse_op, kScratchReg, true); \
__ AtomicCompareExchange<_type>( \
MemOperand(i.InputRegister(0), i.InputRegister(1)), expected_val, \
new_val, dst, kScratchReg); \
MAYBE_REVERSE_IF_WASM(dst, dst, reverse_op, kScratchReg, false); \
} while (false)

Definition at line 621 of file code-generator-ppc.cc.

◆ ASSEMBLE_ATOMIC_EXCHANGE

#define ASSEMBLE_ATOMIC_EXCHANGE ( _type,
reverse_op )
Value:
do { \
Register val = i.InputRegister(2); \
Register dst = i.OutputRegister(); \
MAYBE_REVERSE_IF_WASM(ip, val, reverse_op, kScratchReg, true); \
__ AtomicExchange<_type>( \
MemOperand(i.InputRegister(0), i.InputRegister(1)), val, dst); \
MAYBE_REVERSE_IF_WASM(dst, dst, reverse_op, kScratchReg, false); \
} while (false)

Definition at line 611 of file code-generator-ppc.cc.

◆ ASSEMBLE_BINOP

#define ASSEMBLE_BINOP ( asm_instr_reg,
asm_instr_imm )
Value:
do { \
if (HasRegisterInput(instr, 1)) { \
__ asm_instr_reg(i.OutputRegister(), i.InputRegister(0), \
i.InputRegister(1)); \
} else { \
__ asm_instr_imm(i.OutputRegister(), i.InputRegister(0), \
i.InputImmediate(1)); \
} \
} while (0)

Definition at line 325 of file code-generator-ppc.cc.

◆ ASSEMBLE_BINOP_INT_RC

#define ASSEMBLE_BINOP_INT_RC ( asm_instr_reg,
asm_instr_imm )
Value:
do { \
if (HasRegisterInput(instr, 1)) { \
__ asm_instr_reg(i.OutputRegister(), i.InputRegister(0), \
i.InputRegister(1), i.OutputRCBit()); \
} else { \
__ asm_instr_imm(i.OutputRegister(), i.InputRegister(0), \
i.InputImmediate(1), i.OutputRCBit()); \
} \
} while (0)

Definition at line 347 of file code-generator-ppc.cc.

◆ ASSEMBLE_BINOP_RC

#define ASSEMBLE_BINOP_RC ( asm_instr_reg,
asm_instr_imm )
Value:
do { \
if (HasRegisterInput(instr, 1)) { \
__ asm_instr_reg(i.OutputRegister(), i.InputRegister(0), \
i.InputRegister(1), i.OutputRCBit()); \
} else { \
__ asm_instr_imm(i.OutputRegister(), i.InputRegister(0), \
i.InputImmediate(1), i.OutputRCBit()); \
} \
} while (0)

Definition at line 336 of file code-generator-ppc.cc.

◆ ASSEMBLE_COMPARE

#define ASSEMBLE_COMPARE ( cmp_instr,
cmpl_instr )
Value:
do { \
const CRegister cr = cr0; \
if (HasRegisterInput(instr, 1)) { \
if (i.CompareLogical()) { \
__ cmpl_instr(i.InputRegister(0), i.InputRegister(1), cr); \
} else { \
__ cmp_instr(i.InputRegister(0), i.InputRegister(1), cr); \
} \
} else { \
if (i.CompareLogical()) { \
__ cmpl_instr##i(i.InputRegister(0), i.InputImmediate(1), cr); \
} else { \
__ cmp_instr##i(i.InputRegister(0), i.InputImmediate(1), cr); \
} \
} \
DCHECK_EQ(SetRC, i.OutputRCBit()); \
} while (0)

Definition at line 392 of file code-generator-ppc.cc.

◆ ASSEMBLE_FLOAT_BINOP_RC

#define ASSEMBLE_FLOAT_BINOP_RC ( asm_instr,
round )
Value:
do { \
__ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), \
i.InputDoubleRegister(1), i.OutputRCBit()); \
if (round) { \
__ frsp(i.OutputDoubleRegister(), i.OutputDoubleRegister()); \
} \
} while (0)

Definition at line 316 of file code-generator-ppc.cc.

◆ ASSEMBLE_FLOAT_COMPARE

#define ASSEMBLE_FLOAT_COMPARE ( cmp_instr)
Value:
do { \
const CRegister cr = cr0; \
__ cmp_instr(i.InputDoubleRegister(0), i.InputDoubleRegister(1), cr); \
DCHECK_EQ(SetRC, i.OutputRCBit()); \
} while (0)

Definition at line 411 of file code-generator-ppc.cc.

◆ ASSEMBLE_FLOAT_MODULO

#define ASSEMBLE_FLOAT_MODULO ( )
Value:
do { \
FrameScope scope(masm(), StackFrame::MANUAL); \
__ PrepareCallCFunction(0, 2, kScratchReg); \
__ MovToFloatParameters(i.InputDoubleRegister(0), \
i.InputDoubleRegister(1)); \
__ CallCFunction(ExternalReference::mod_two_doubles_operation(), 0, 2); \
__ MovFromFloatResult(i.OutputDoubleRegister()); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)

Definition at line 427 of file code-generator-ppc.cc.

◆ ASSEMBLE_FLOAT_UNOP_RC

#define ASSEMBLE_FLOAT_UNOP_RC ( asm_instr,
round )
Value:
do { \
__ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), \
i.OutputRCBit()); \
if (round) { \
__ frsp(i.OutputDoubleRegister(), i.OutputDoubleRegister()); \
} \
} while (0)

Definition at line 307 of file code-generator-ppc.cc.

◆ ASSEMBLE_IEEE754_BINOP

#define ASSEMBLE_IEEE754_BINOP ( name)
Value:
do { \
/* TODO(bmeurer): We should really get rid of this special instruction, */ \
/* and generate a CallAddress instruction instead. */ \
FrameScope scope(masm(), StackFrame::MANUAL); \
__ PrepareCallCFunction(0, 2, kScratchReg); \
__ MovToFloatParameters(i.InputDoubleRegister(0), \
i.InputDoubleRegister(1)); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 2); \
/* Move the result in the double result register. */ \
__ MovFromFloatResult(i.OutputDoubleRegister()); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)

Definition at line 451 of file code-generator-ppc.cc.

◆ ASSEMBLE_IEEE754_UNOP

#define ASSEMBLE_IEEE754_UNOP ( name)
Value:
do { \
/* TODO(bmeurer): We should really get rid of this special instruction, */ \
/* and generate a CallAddress instruction instead. */ \
FrameScope scope(masm(), StackFrame::MANUAL); \
__ PrepareCallCFunction(0, 1, kScratchReg); \
__ MovToFloatParameter(i.InputDoubleRegister(0)); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 1); \
/* Move the result in the double result register. */ \
__ MovFromFloatResult(i.OutputDoubleRegister()); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)

Definition at line 438 of file code-generator-ppc.cc.

◆ ASSEMBLE_LOAD_FLOAT

#define ASSEMBLE_LOAD_FLOAT ( asm_instr,
asm_instrp,
asm_instrx )
Value:
do { \
DoubleRegister result = i.OutputDoubleRegister(); \
size_t index = 0; \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, &index); \
bool is_atomic = i.InputInt32(index); \
if (mode == kMode_MRI) { \
intptr_t offset = operand.offset(); \
if (is_int16(offset)) { \
__ asm_instr(result, operand); \
} else { \
CHECK(CpuFeatures::IsSupported(PPC_10_PLUS)); \
__ asm_instrp(result, operand); \
} \
} else { \
__ asm_instrx(result, operand); \
} \
if (is_atomic) __ lwsync(); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)
offset
int32_t offset
Definition instruction-selector-ia32.cc:67
result
ZoneVector< RpoNumber > & result
Definition jump-threading.cc:21

Definition at line 465 of file code-generator-ppc.cc.

◆ ASSEMBLE_LOAD_INTEGER

#define ASSEMBLE_LOAD_INTEGER ( asm_instr,
asm_instrp,
asm_instrx,
must_be_aligned )
Value:
do { \
Register result = i.OutputRegister(); \
size_t index = 0; \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, &index); \
bool is_atomic = i.InputInt32(index); \
if (mode == kMode_MRI) { \
intptr_t offset = operand.offset(); \
bool misaligned = offset & 3; \
if (is_int16(offset) && (!must_be_aligned || !misaligned)) { \
__ asm_instr(result, operand); \
} else { \
CHECK(CpuFeatures::IsSupported(PPC_10_PLUS)); \
__ asm_instrp(result, operand); \
} \
} else { \
__ asm_instrx(result, operand); \
} \
if (is_atomic) __ lwsync(); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)

Definition at line 487 of file code-generator-ppc.cc.

◆ ASSEMBLE_LOAD_INTEGER_RR

#define ASSEMBLE_LOAD_INTEGER_RR ( asm_instr)
Value:
do { \
Register result = i.OutputRegister(); \
size_t index = 0; \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, &index); \
DCHECK_EQ(mode, kMode_MRR); \
bool is_atomic = i.InputInt32(index); \
__ asm_instr(result, operand); \
if (is_atomic) __ lwsync(); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)

Definition at line 511 of file code-generator-ppc.cc.

◆ ASSEMBLE_MODULO

#define ASSEMBLE_MODULO ( div_instr,
mul_instr )
Value:
do { \
const Register scratch = kScratchReg; \
__ div_instr(scratch, i.InputRegister(0), i.InputRegister(1)); \
__ mul_instr(scratch, scratch, i.InputRegister(1)); \
__ sub(i.OutputRegister(), i.InputRegister(0), scratch, LeaveOE, \
i.OutputRCBit()); \
} while (0)

Definition at line 418 of file code-generator-ppc.cc.

◆ ASSEMBLE_STORE_FLOAT

#define ASSEMBLE_STORE_FLOAT ( asm_instr,
asm_instrp,
asm_instrx )
Value:
do { \
size_t index = 0; \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, &index); \
DoubleRegister value = i.InputDoubleRegister(index); \
bool is_atomic = i.InputInt32(3); \
if (is_atomic) __ lwsync(); \
/* removed frsp as instruction-selector checked */ \
/* value to be kFloat32 */ \
if (mode == kMode_MRI) { \
intptr_t offset = operand.offset(); \
if (is_int16(offset)) { \
__ asm_instr(value, operand); \
} else { \
CHECK(CpuFeatures::IsSupported(PPC_10_PLUS)); \
__ asm_instrp(value, operand); \
} \
} else { \
__ asm_instrx(value, operand); \
} \
if (is_atomic) __ sync(); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)

Definition at line 524 of file code-generator-ppc.cc.

◆ ASSEMBLE_STORE_INTEGER

#define ASSEMBLE_STORE_INTEGER ( asm_instr,
asm_instrp,
asm_instrx,
must_be_aligned )
Value:
do { \
size_t index = 0; \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, &index); \
Register value = i.InputRegister(index); \
bool is_atomic = i.InputInt32(index + 1); \
if (is_atomic) __ lwsync(); \
if (mode == kMode_MRI) { \
intptr_t offset = operand.offset(); \
bool misaligned = offset & 3; \
if (is_int16(offset) && (!must_be_aligned || !misaligned)) { \
__ asm_instr(value, operand); \
} else { \
CHECK(CpuFeatures::IsSupported(PPC_10_PLUS)); \
__ asm_instrp(value, operand); \
} \
} else { \
__ asm_instrx(value, operand); \
} \
if (is_atomic) __ sync(); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)

Definition at line 549 of file code-generator-ppc.cc.

◆ ASSEMBLE_STORE_INTEGER_RR

#define ASSEMBLE_STORE_INTEGER_RR ( asm_instr)
Value:
do { \
size_t index = 0; \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode, &index); \
DCHECK_EQ(mode, kMode_MRR); \
Register value = i.InputRegister(index); \
bool is_atomic = i.InputInt32(index + 1); \
if (is_atomic) __ lwsync(); \
__ asm_instr(value, operand); \
if (is_atomic) __ sync(); \
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
} while (0)

Definition at line 574 of file code-generator-ppc.cc.

◆ ASSEMBLE_SUB_WITH_OVERFLOW

#define ASSEMBLE_SUB_WITH_OVERFLOW ( )
Value:
do { \
if (HasRegisterInput(instr, 1)) { \
__ SubAndCheckForOverflow(i.OutputRegister(), i.InputRegister(0), \
i.InputRegister(1), kScratchReg, r0); \
} else { \
__ AddAndCheckForOverflow(i.OutputRegister(), i.InputRegister(0), \
-i.InputInt32(1), kScratchReg, r0); \
} \
} while (0)

Definition at line 369 of file code-generator-ppc.cc.

◆ ASSEMBLE_SUB_WITH_OVERFLOW32

#define ASSEMBLE_SUB_WITH_OVERFLOW32 ( )
Value:
do { \
ASSEMBLE_SUB_WITH_OVERFLOW(); \
__ extsw(kScratchReg, kScratchReg, SetRC); \
} while (0)

Definition at line 386 of file code-generator-ppc.cc.

◆ ATOMIC_BINOP_CASE

#define ATOMIC_BINOP_CASE ( op,
inst )
Value:
case kPPC_Atomic##op##Int8: \
ASSEMBLE_ATOMIC_BINOP_BYTE(inst, int8_t); \
__ extsb(i.OutputRegister(), i.OutputRegister()); \
break; \
case kPPC_Atomic##op##Uint8: \
ASSEMBLE_ATOMIC_BINOP_BYTE(inst, uint8_t); \
break; \
case kPPC_Atomic##op##Int16: \
ASSEMBLE_ATOMIC_BINOP(inst, int16_t, ByteReverseU16, r0); \
__ extsh(i.OutputRegister(), i.OutputRegister()); \
break; \
case kPPC_Atomic##op##Uint16: \
ASSEMBLE_ATOMIC_BINOP(inst, uint16_t, ByteReverseU16, r0); \
break; \
case kPPC_Atomic##op##Int32: \
ASSEMBLE_ATOMIC_BINOP(inst, int32_t, ByteReverseU32, r0); \
__ extsw(i.OutputRegister(), i.OutputRegister()); \
break; \
case kPPC_Atomic##op##Uint32: \
ASSEMBLE_ATOMIC_BINOP(inst, uint32_t, ByteReverseU32, r0); \
break; \
case kPPC_Atomic##op##Int64: \
case kPPC_Atomic##op##Uint64: \
ASSEMBLE_ATOMIC_BINOP(inst, uint64_t, ByteReverseU64, r0); \
break;

◆ CleanUInt32

#define CleanUInt32 ( x)
Value:
__ ClearLeftImm(x, x, Operand(32))
x
int x
Definition liveedit-diff.cc:60
ClearLeftImm
#define ClearLeftImm
Definition macro-assembler-ppc.h:43

Definition at line 589 of file code-generator-ppc.cc.

◆ DOUBLE_TO_INT32

#define DOUBLE_TO_INT32 ( op)
Value:
bool check_conversion = i.OutputCount() > 1; \
CRegister cr = cr0; \
FPSCRBit fps_bit = VXCVI; \
int cr_bit = v8::internal::Assembler::encode_crbit( \
cr, static_cast<CRBit>(fps_bit % CRWIDTH)); \
__ mtfsb0(fps_bit); /* clear FPSCR:VXCVI bit */ \
__ op(kScratchDoubleReg, i.InputDoubleRegister(0)); \
__ MovDoubleLowToInt(i.OutputRegister(0), kScratchDoubleReg); \
__ mcrfs(cr, VXCVI); /* extract FPSCR field containing VXCVI into cr0 */ \
if (check_conversion) { \
__ li(i.OutputRegister(1), Operand(1)); \
__ isel(i.OutputRegister(1), r0, i.OutputRegister(1), cr_bit); \
} else { \
__ isel(i.OutputRegister(0), r0, i.OutputRegister(0), cr_bit); \
}
v8::internal::Assembler::encode_crbit
static int encode_crbit(const CRegister &cr, enum CRBit crbit)
Definition assembler-ppc.h:320
CRWIDTH
#define CRWIDTH
Definition constants-ppc.h:2907

◆ EMIT_SIMD_ALL_TRUE

#define EMIT_SIMD_ALL_TRUE ( name)
Value:
case kPPC_##name: { \
__ name(i.OutputRegister(), i.InputSimd128Register(0), r0, ip, \
kScratchSimd128Reg); \
break; \
}
name
const char * name
Definition builtins.cc:39

◆ EMIT_SIMD_BINOP

#define EMIT_SIMD_BINOP ( name)
Value:
case kPPC_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1)); \
break; \
}

◆ EMIT_SIMD_BINOP_WITH_SCRATCH

#define EMIT_SIMD_BINOP_WITH_SCRATCH ( name)
Value:
case kPPC_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1), kScratchSimd128Reg); \
break; \
}

◆ EMIT_SIMD_EXT_ADD_PAIRWISE

#define EMIT_SIMD_EXT_ADD_PAIRWISE ( name)
Value:
case kPPC_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
kScratchSimd128Reg, kScratchSimd128Reg2); \
break; \
}

◆ EMIT_SIMD_LOAD_LANE

#define EMIT_SIMD_LOAD_LANE ( name,
op )
Value:
case kPPC_##name: { \
Simd128Register dst = i.OutputSimd128Register(); \
DCHECK_EQ(dst, i.InputSimd128Register(0)); \
AddressingMode mode = kMode_None; \
size_t index = 1; \
MemOperand operand = i.MemoryOperand(&mode, &index); \
DCHECK_EQ(mode, kMode_MRR); \
__ op(dst, operand, i.InputUint8(3), kScratchReg, kScratchSimd128Reg); \
break; \
}

◆ EMIT_SIMD_LOAD_SPLAT

#define EMIT_SIMD_LOAD_SPLAT ( name,
op )
Value:
case kPPC_##name: { \
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode); \
DCHECK_EQ(mode, kMode_MRR); \
__ op(i.OutputSimd128Register(), operand, kScratchReg); \
break; \
}

◆ EMIT_SIMD_QFM

#define EMIT_SIMD_QFM ( name)
Value:
case kPPC_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1), i.InputSimd128Register(2), \
kScratchSimd128Reg); \
break; \
}

◆ EMIT_SIMD_SHIFT

#define EMIT_SIMD_SHIFT ( name)
Value:
case kPPC_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputRegister(1), kScratchSimd128Reg); \
break; \
}

◆ EMIT_SIMD_STORE_LANE

#define EMIT_SIMD_STORE_LANE ( name,
op )
Value:
case kPPC_##name: { \
AddressingMode mode = kMode_None; \
size_t index = 1; \
MemOperand operand = i.MemoryOperand(&mode, &index); \
DCHECK_EQ(mode, kMode_MRR); \
__ op(i.InputSimd128Register(0), operand, i.InputUint8(3), kScratchReg, \
kScratchSimd128Reg); \
break; \
}

◆ EMIT_SIMD_UNOP

#define EMIT_SIMD_UNOP ( name)
Value:
case kPPC_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
break; \
}

◆ EMIT_SIMD_UNOP_WITH_SCRATCH

#define EMIT_SIMD_UNOP_WITH_SCRATCH ( name)
Value:
case kPPC_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
kScratchSimd128Reg); \
break; \
}

◆ kScratchReg

#define kScratchReg   r11

Definition at line 29 of file code-generator-ppc.cc.

◆ MAYBE_REVERSE_IF_WASM

#define MAYBE_REVERSE_IF_WASM ( dst,
src,
op,
scratch,
reset )

Definition at line 608 of file code-generator-ppc.cc.

◆ PREP_LOAD_EXTEND

#define PREP_LOAD_EXTEND ( )
Value:
AddressingMode mode = kMode_None; \
MemOperand operand = i.MemoryOperand(&mode); \
DCHECK_EQ(mode, kMode_MRR);

◆ SIMD_ALL_TRUE_LIST

#define SIMD_ALL_TRUE_LIST ( V)
Value:
V(I64x2AllTrue) \
V(I32x4AllTrue) \
V(I16x8AllTrue) \
V(I8x16AllTrue)
V
#define V(Name)

◆ SIMD_BINOP_LIST

#define SIMD_BINOP_LIST ( V)

◆ SIMD_BINOP_WITH_SCRATCH_LIST

#define SIMD_BINOP_WITH_SCRATCH_LIST ( V)

◆ SIMD_EXT_ADD_PAIRWISE_LIST

#define SIMD_EXT_ADD_PAIRWISE_LIST ( V)
Value:
V(I32x4ExtAddPairwiseI16x8S) \
V(I32x4ExtAddPairwiseI16x8U) \
V(I16x8ExtAddPairwiseI8x16S) \
V(I16x8ExtAddPairwiseI8x16U)

◆ SIMD_LOAD_LANE_LIST

#define SIMD_LOAD_LANE_LIST ( V)
Value:
V(S128Load64Lane, LoadLane64LE) \
V(S128Load32Lane, LoadLane32LE) \
V(S128Load16Lane, LoadLane16LE) \
V(S128Load8Lane, LoadLane8LE)

◆ SIMD_LOAD_SPLAT

#define SIMD_LOAD_SPLAT ( V)
Value:
V(S128Load64Splat, LoadAndSplat64x2LE) \
V(S128Load32Splat, LoadAndSplat32x4LE) \
V(S128Load16Splat, LoadAndSplat16x8LE) \
V(S128Load8Splat, LoadAndSplat8x16LE)

◆ SIMD_QFM_LIST

#define SIMD_QFM_LIST ( V)
Value:
V(F64x2Qfma) \
V(F64x2Qfms) \
V(F32x4Qfma) \
V(F32x4Qfms)

◆ SIMD_SHIFT_LIST

#define SIMD_SHIFT_LIST ( V)
Value:
V(I64x2Shl) \
V(I64x2ShrS) \
V(I64x2ShrU) \
V(I32x4Shl) \
V(I32x4ShrS) \
V(I32x4ShrU) \
V(I16x8Shl) \
V(I16x8ShrS) \
V(I16x8ShrU) \
V(I8x16Shl) \
V(I8x16ShrS) \
V(I8x16ShrU)

◆ SIMD_STORE_LANE_LIST

#define SIMD_STORE_LANE_LIST ( V)
Value:
V(S128Store64Lane, StoreLane64LE) \
V(S128Store32Lane, StoreLane32LE) \
V(S128Store16Lane, StoreLane16LE) \
V(S128Store8Lane, StoreLane8LE)

◆ SIMD_UNOP_LIST

#define SIMD_UNOP_LIST ( V)
Value:
V(F64x2Abs) \
V(F64x2Neg) \
V(F64x2Sqrt) \
V(F64x2Ceil) \
V(F64x2Floor) \
V(F64x2Trunc) \
V(F64x2PromoteLowF32x4) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4SConvertI32x4) \
V(F32x4UConvertI32x4) \
V(I64x2Neg) \
V(I32x4Neg) \
V(F32x4Sqrt) \
V(F32x4Ceil) \
V(F32x4Floor) \
V(F32x4Trunc) \
V(F64x2ConvertLowI32x4S) \
V(I64x2SConvertI32x4Low) \
V(I64x2SConvertI32x4High) \
V(I32x4SConvertI16x8Low) \
V(I32x4SConvertI16x8High) \
V(I32x4UConvertF32x4) \
V(I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High) \
V(I8x16Popcnt) \
V(S128Not)

◆ SIMD_UNOP_WITH_SCRATCH_LIST

#define SIMD_UNOP_WITH_SCRATCH_LIST ( V)
Value:
V(F32x4DemoteF64x2Zero) \
V(I64x2Abs) \
V(I32x4Abs) \
V(I32x4SConvertF32x4) \
V(I32x4TruncSatF64x2SZero) \
V(I32x4TruncSatF64x2UZero) \
V(I16x8Abs) \
V(I16x8Neg) \
V(I8x16Abs) \
V(I8x16Neg)

Variable Documentation

◆ indirect_pointer_tag_

IndirectPointerTag indirect_pointer_tag_
private

Definition at line 253 of file code-generator-ppc.cc.

◆ mode_

RecordWriteMode const mode_
private

Definition at line 246 of file code-generator-ppc.cc.

◆ must_save_lr_

bool must_save_lr_
private

Definition at line 250 of file code-generator-ppc.cc.

◆ object_

Register const object_
private

Definition at line 240 of file code-generator-ppc.cc.

◆ offset_

Register const offset_
private

Definition at line 241 of file code-generator-ppc.cc.

◆ offset_immediate_

int32_t const offset_immediate_
private

Definition at line 242 of file code-generator-ppc.cc.

◆ scratch0_

Register const scratch0_
private

Definition at line 244 of file code-generator-ppc.cc.

◆ scratch1_

Register const scratch1_
private

Definition at line 245 of file code-generator-ppc.cc.

◆ unwinding_info_writer_

UnwindingInfoWriter* const unwinding_info_writer_
private

Definition at line 251 of file code-generator-ppc.cc.

◆ value_

Register const value_
private

Definition at line 243 of file code-generator-ppc.cc.

◆ zone_

Zone* zone_
private

Definition at line 252 of file code-generator-ppc.cc.