42#ifdef V8_TARGET_ARCH_RISCV64
49void AssemblerRISCVM::divw(Register rd, Register rs1, Register rs2) {
53void AssemblerRISCVM::divuw(Register rd, Register rs1, Register rs2) {
57void AssemblerRISCVM::remw(Register rd, Register rs1, Register rs2) {
61void AssemblerRISCVM::remuw(Register rd, Register rs1, Register rs2) {
void mulhu(Register rd, Register rs1, Register rs2)
void divu(Register rd, Register rs1, Register rs2)
void mulh(Register rd, Register rs1, Register rs2)
void mulhsu(Register rd, Register rs1, Register rs2)
void rem(Register rd, Register rs1, Register rs2)
void remu(Register rd, Register rs1, Register rs2)
void mul(Register rd, Register rs1, Register rs2)
void div(Register rd, Register rs1, Register rs2)
void GenInstrALUW_rr(uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2)
void GenInstrALU_rr(uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2)