v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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instruction-selector-ppc.cc File Reference
#include <optional>
#include "src/base/iterator.h"
#include "src/compiler/backend/instruction-selector-impl.h"
#include "src/compiler/turboshaft/opmasks.h"
#include "src/execution/ppc/frame-constants-ppc.h"
#include "src/roots/roots-inl.h"
Include dependency graph for instruction-selector-ppc.cc:

Go to the source code of this file.

Classes

class  v8::internal::compiler::PPCOperandGeneratorT
 

Namespaces

namespace  v8
 
namespace  v8::internal
 
namespace  v8::internal::compiler
 

Macros

#define VISIT_ATOMIC_BINOP(op)
 
#define SIMD_TYPES(V)
 
#define SIMD_BINOP_LIST(V)
 
#define SIMD_UNOP_LIST(V)
 
#define SIMD_VISIT_SPLAT(Type, T, LaneSize)
 
#define SIMD_VISIT_EXTRACT_LANE(Type, T, Sign, LaneSize)
 
#define SIMD_VISIT_REPLACE_LANE(Type, T, LaneSize)
 
#define SIMD_VISIT_BINOP(Opcode)
 
#define SIMD_VISIT_UNOP(Opcode)
 
#define SIMD_VISIT_QFMOP(Opcode)
 
#define SIMD_RELAXED_OP_LIST(V)
 
#define SIMD_VISIT_RELAXED_OP(name, op)
 
#define F16_OP_LIST(V)
 
#define VISIT_F16_OP(name)
 

Enumerations

enum  v8::internal::compiler::ImmediateMode {
  v8::internal::compiler::kArithmeticImm , v8::internal::compiler::kShift32Imm , v8::internal::compiler::kShift64Imm , v8::internal::compiler::kLogical32Imm ,
  v8::internal::compiler::kLogical64Imm , v8::internal::compiler::kLoadStoreImm8 , v8::internal::compiler::kLoadStoreImm16 , v8::internal::compiler::kLoadStoreImm32 ,
  v8::internal::compiler::kLoadStoreImm64 , v8::internal::compiler::kConditionalCompareImm , v8::internal::compiler::kNoImmediate , v8::internal::compiler::kInt16Imm ,
  v8::internal::compiler::kInt16Imm_Unsigned , v8::internal::compiler::kInt16Imm_Negate , v8::internal::compiler::kInt16Imm_4ByteAligned , v8::internal::compiler::kShift32Imm ,
  v8::internal::compiler::kInt34Imm , v8::internal::compiler::kShift64Imm , v8::internal::compiler::kNoImmediate
}
 

Functions

ArchOpcode v8::internal::compiler::SelectLoadOpcode (MemoryRepresentation loaded_rep, RegisterRepresentation result_rep, ImmediateMode *mode)
 
ArchOpcode v8::internal::compiler::SelectLoadOpcode (LoadRepresentation load_rep, ImmediateMode *mode)
 
static void v8::internal::compiler::VisitLoadCommon (InstructionSelectorT *selector, OpIndex node, ImmediateMode mode, InstructionCode opcode)
 
void v8::internal::compiler::VisitStoreCommon (InstructionSelectorT *selector, OpIndex node, StoreRepresentation store_rep, std::optional< AtomicMemoryOrder > atomic_order)
 
static void v8::internal::compiler::VisitLogical (InstructionSelectorT *selector, OpIndex node, ArchOpcode opcode, bool left_can_cover, bool right_can_cover, ImmediateMode imm_mode)
 
static bool v8::internal::compiler::IsContiguousMask32 (uint32_t value, int *mb, int *me)
 
static bool v8::internal::compiler::IsContiguousMask64 (uint64_t value, int *mb, int *me)
 
static bool v8::internal::compiler::CompareLogical (FlagsContinuationT *cont)
 
void v8::internal::compiler::VisitAtomicExchange (InstructionSelectorT *selector, OpIndex node, ArchOpcode opcode)
 
void v8::internal::compiler::VisitAtomicCompareExchange (InstructionSelectorT *selector, OpIndex node, ArchOpcode opcode)
 
void v8::internal::compiler::VisitAtomicBinaryOperation (InstructionSelectorT *selector, OpIndex node, ArchOpcode int8_op, ArchOpcode uint8_op, ArchOpcode int16_op, ArchOpcode uint16_op, ArchOpcode int32_op, ArchOpcode uint32_op, ArchOpcode int64_op, ArchOpcode uint64_op)
 
static int32_t v8::internal::compiler::Pack4Lanes (const uint8_t *shuffle)
 

Macro Definition Documentation

◆ F16_OP_LIST

#define F16_OP_LIST ( V)

Definition at line 2597 of file instruction-selector-ppc.cc.

◆ SIMD_BINOP_LIST

#define SIMD_BINOP_LIST ( V)

Definition at line 2313 of file instruction-selector-ppc.cc.

◆ SIMD_RELAXED_OP_LIST

#define SIMD_RELAXED_OP_LIST ( V)
Value:
V(F64x2RelaxedMin, F64x2Pmin) \
V(F64x2RelaxedMax, F64x2Pmax) \
V(F32x4RelaxedMin, F32x4Pmin) \
V(F32x4RelaxedMax, F32x4Pmax) \
V(I32x4RelaxedTruncF32x4S, I32x4SConvertF32x4) \
V(I32x4RelaxedTruncF32x4U, I32x4UConvertF32x4) \
V(I32x4RelaxedTruncF64x2SZero, I32x4TruncSatF64x2SZero) \
V(I32x4RelaxedTruncF64x2UZero, I32x4TruncSatF64x2UZero) \
V(I16x8RelaxedQ15MulRS, I16x8Q15MulRSatS) \
V(I8x16RelaxedLaneSelect, S128Select) \
V(I16x8RelaxedLaneSelect, S128Select) \
V(I32x4RelaxedLaneSelect, S128Select) \
V(I64x2RelaxedLaneSelect, S128Select)
V
#define V(Name)

Definition at line 2576 of file instruction-selector-ppc.cc.

◆ SIMD_TYPES

#define SIMD_TYPES ( V)
Value:
V(F64x2) \
V(F32x4) \
V(I64x2) \
V(I32x4) \
V(I16x8) \
V(I8x16)

Definition at line 2305 of file instruction-selector-ppc.cc.

◆ SIMD_UNOP_LIST

#define SIMD_UNOP_LIST ( V)

Definition at line 2429 of file instruction-selector-ppc.cc.

◆ SIMD_VISIT_BINOP

#define SIMD_VISIT_BINOP ( Opcode)
Value:
void InstructionSelectorT::Visit##Opcode(OpIndex node) { \
PPCOperandGeneratorT g(this); \
InstructionOperand temps[] = {g.TempRegister()}; \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(this->input_at(node, 0)), \
g.UseRegister(this->input_at(node, 1)), arraysize(temps), temps); \
}
arraysize
#define arraysize(array)
Definition macros.h:67

Definition at line 2540 of file instruction-selector-ppc.cc.

◆ SIMD_VISIT_EXTRACT_LANE

#define SIMD_VISIT_EXTRACT_LANE ( Type,
T,
Sign,
LaneSize )
Value:
void InstructionSelectorT::Visit##Type##ExtractLane##Sign(OpIndex node) { \
PPCOperandGeneratorT g(this); \
int32_t lane; \
const Operation& op = this->Get(node); \
lane = op.template Cast<Simd128ExtractLaneOp>().lane; \
Emit(kPPC_##T##ExtractLane##Sign | LaneSizeField::encode(LaneSize), \
g.DefineAsRegister(node), g.UseRegister(this->input_at(node, 0)), \
g.UseImmediate(lane)); \
}
Operation
Operation
Definition operation.h:43

Definition at line 2502 of file instruction-selector-ppc.cc.

◆ SIMD_VISIT_QFMOP

#define SIMD_VISIT_QFMOP ( Opcode)
Value:
void InstructionSelectorT::Visit##Opcode(OpIndex node) { \
PPCOperandGeneratorT g(this); \
Emit(kPPC_##Opcode, g.DefineSameAsFirst(node), \
g.UseRegister(this->input_at(node, 0)), \
g.UseRegister(this->input_at(node, 1)), \
g.UseRegister(this->input_at(node, 2))); \
}

Definition at line 2562 of file instruction-selector-ppc.cc.

◆ SIMD_VISIT_RELAXED_OP

#define SIMD_VISIT_RELAXED_OP ( name,
op )
Value:
void InstructionSelectorT::Visit##name(OpIndex node) { Visit##op(node); }
name
const char * name
Definition builtins.cc:39

Definition at line 2591 of file instruction-selector-ppc.cc.

◆ SIMD_VISIT_REPLACE_LANE

#define SIMD_VISIT_REPLACE_LANE ( Type,
T,
LaneSize )
Value:
void InstructionSelectorT::Visit##Type##ReplaceLane(OpIndex node) { \
PPCOperandGeneratorT g(this); \
int32_t lane; \
const Operation& op = this->Get(node); \
lane = op.template Cast<Simd128ReplaceLaneOp>().lane; \
Emit(kPPC_##T##ReplaceLane | LaneSizeField::encode(LaneSize), \
g.DefineSameAsFirst(node), g.UseRegister(this->input_at(node, 0)), \
g.UseImmediate(lane), g.UseRegister(this->input_at(node, 1))); \
}

Definition at line 2522 of file instruction-selector-ppc.cc.

◆ SIMD_VISIT_SPLAT

#define SIMD_VISIT_SPLAT ( Type,
T,
LaneSize )
Value:
void InstructionSelectorT::Visit##Type##Splat(OpIndex node) { \
PPCOperandGeneratorT g(this); \
Emit(kPPC_##T##Splat | LaneSizeField::encode(LaneSize), \
g.DefineAsRegister(node), g.UseRegister(this->input_at(node, 0))); \
}

Definition at line 2488 of file instruction-selector-ppc.cc.

◆ SIMD_VISIT_UNOP

#define SIMD_VISIT_UNOP ( Opcode)
Value:
void InstructionSelectorT::Visit##Opcode(OpIndex node) { \
PPCOperandGeneratorT g(this); \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(this->input_at(node, 0))); \
}

Definition at line 2552 of file instruction-selector-ppc.cc.

◆ VISIT_ATOMIC_BINOP

#define VISIT_ATOMIC_BINOP ( op)
Value:
void InstructionSelectorT::VisitWord32Atomic##op(OpIndex node) { \
VisitAtomicBinaryOperation( \
this, node, kPPC_Atomic##op##Int8, kPPC_Atomic##op##Uint8, \
kPPC_Atomic##op##Int16, kPPC_Atomic##op##Uint16, \
kPPC_Atomic##op##Int32, kPPC_Atomic##op##Uint32, \
kPPC_Atomic##op##Int64, kPPC_Atomic##op##Uint64); \
} \
void InstructionSelectorT::VisitWord64Atomic##op(OpIndex node) { \
VisitAtomicBinaryOperation( \
this, node, kPPC_Atomic##op##Int8, kPPC_Atomic##op##Uint8, \
kPPC_Atomic##op##Int16, kPPC_Atomic##op##Uint16, \
kPPC_Atomic##op##Int32, kPPC_Atomic##op##Uint32, \
kPPC_Atomic##op##Int64, kPPC_Atomic##op##Uint64); \
}

Definition at line 2275 of file instruction-selector-ppc.cc.

◆ VISIT_F16_OP

#define VISIT_F16_OP ( name)
Value:
void InstructionSelectorT::Visit##name(OpIndex node) { UNIMPLEMENTED(); }
UNIMPLEMENTED
#define UNIMPLEMENTED()
Definition logging.h:66

Definition at line 2630 of file instruction-selector-ppc.cc.