liftoff-assembler-riscv64-inl.h File Reference

#include "src/codegen/interface-descriptors-inl.h"
#include "src/heap/mutable-page-metadata.h"
#include "src/wasm/baseline/liftoff-assembler.h"
#include "src/wasm/baseline/riscv/liftoff-assembler-riscv-inl.h"
#include "src/wasm/wasm-objects.h"

Include dependency graph for liftoff-assembler-riscv64-inl.h:

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Namespaces
namespace	v8
namespace	v8::internal
namespace	v8::internal::wasm
namespace	v8::internal::wasm::liftoff

Macros
#define	__   lasm->
#define	ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(load_linked, store_conditional)
#define	ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT( load_linked, store_conditional, size, aligned)
#define	I32_BINOP(name, instruction)
#define	I32_BINOP_I(name, instruction)
#define	I32_SHIFTOP(name, instruction)
#define	I32_SHIFTOP_I(name, instruction)
#define	I64_BINOP(name, instruction)
#define	I64_BINOP_I(name, instruction)
#define	I64_SHIFTOP(name, instruction)
#define	FP_UNOP_RETURN_TRUE(name, instruction)

Enumerations
enum class	v8::internal::wasm::liftoff::Binop {   v8::internal::wasm::liftoff::kAdd , v8::internal::wasm::liftoff::kSub , v8::internal::wasm::liftoff::kAnd , v8::internal::wasm::liftoff::kOr ,   v8::internal::wasm::liftoff::kXor , v8::internal::wasm::liftoff::kExchange , v8::internal::wasm::liftoff::kAdd , v8::internal::wasm::liftoff::kSub ,   v8::internal::wasm::liftoff::kAnd , v8::internal::wasm::liftoff::kOr , v8::internal::wasm::liftoff::kXor , v8::internal::wasm::liftoff::kExchange ,   v8::internal::wasm::liftoff::kAdd , v8::internal::wasm::liftoff::kSub , v8::internal::wasm::liftoff::kAnd , v8::internal::wasm::liftoff::kOr ,   v8::internal::wasm::liftoff::kXor , v8::internal::wasm::liftoff::kExchange }

Functions
MemOperand	v8::internal::wasm::liftoff::GetMemOp (LiftoffAssembler *assm, Register addr, Register offset, uintptr_t offset_imm, bool i64_offset=false, unsigned shift_amount=0)
void	v8::internal::wasm::liftoff::Load (LiftoffAssembler *assm, LiftoffRegister dst, MemOperand src, ValueKind kind)
void	v8::internal::wasm::liftoff::Store (LiftoffAssembler *assm, Register base, int32_t offset, LiftoffRegister src, ValueKind kind)
void	v8::internal::wasm::liftoff::push (LiftoffAssembler *assm, LiftoffRegister reg, ValueKind kind)
void	v8::internal::wasm::liftoff::StoreToMemory (LiftoffAssembler *assm, MemOperand dst, const LiftoffAssembler::VarState &src)
Register	v8::internal::wasm::liftoff::CalculateActualAddress (LiftoffAssembler *lasm, UseScratchRegisterScope &temps, Register addr_reg, Register offset_reg, uintptr_t offset_imm)
void	v8::internal::wasm::liftoff::AtomicBinop (LiftoffAssembler *lasm, Register dst_addr, Register offset_reg, uintptr_t offset_imm, LiftoffRegister value, LiftoffRegister result, StoreType type, Binop op)

Macro Definition Documentation

__

#define __   lasm->

Definition at line 478 of file liftoff-assembler-riscv64-inl.h.

ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER

#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER	(		load_linked,
			store_conditional )

Value:

  do {                                                              \
    Label compareExchange;                                          \
    Label exit;                                                     \
    sync();                                                         \
    bind(&compareExchange);                                         \
    load_linked(result.gp(), MemOperand(temp0, 0));                 \
    BranchShort(&exit, ne, expected.gp(), Operand(result.gp()));    \
    mv(temp2, new_value.gp());                                      \
    store_conditional(temp2, MemOperand(temp0, 0));                 \
    BranchShort(&compareExchange, ne, temp2, Operand(zero_reg));    \
    bind(&exit);                                                    \
    sync();                                                         \
  } while (0)

Definition at line 720 of file liftoff-assembler-riscv64-inl.h.

ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT

#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT	(		load_linked,
			store_conditional,
			size,
			aligned )

Value:

  do {                                                           \
    Label compareExchange;                                       \
    Label exit;                                                  \
    andi(temp1, temp0, aligned);                                 \
    Sub64(temp0, temp0, Operand(temp1));                         \
    Sll32(temp1, temp1, 3);                                      \
    sync();                                                      \
    bind(&compareExchange);                                      \
    load_linked(temp2, MemOperand(temp0, 0));                    \
    ExtractBits(result.gp(), temp2, temp1, size, false);         \
    ExtractBits(temp2, expected.gp(), zero_reg, size, false);    \
    BranchShort(&exit, ne, temp2, Operand(result.gp()));         \
    InsertBits(temp2, new_value.gp(), temp1, size);              \
    store_conditional(temp2, MemOperand(temp0, 0));              \
    BranchShort(&compareExchange, ne, temp2, Operand(zero_reg)); \
    bind(&exit);                                                 \
    sync();                                                      \
  } while (0)

Definition at line 736 of file liftoff-assembler-riscv64-inl.h.

FP_UNOP_RETURN_TRUE

#define FP_UNOP_RETURN_TRUE	(		name,
			instruction )

Value:

  bool LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister src) { \
    instruction(dst, src, kScratchDoubleReg);                                  \
    return true;                                                               \
  }

Definition at line 1274 of file liftoff-assembler-riscv64-inl.h.

I32_BINOP

#define I32_BINOP	(		name,
			instruction )

Value:

  void LiftoffAssembler::emit_i32_##name(Register dst, Register lhs, \
                                         Register rhs) {             \
    instruction(dst, lhs, rhs);                                      \
  }

Definition at line 1063 of file liftoff-assembler-riscv64-inl.h.

I32_BINOP_I

#define I32_BINOP_I	(		name,
			instruction )

Value:

  void LiftoffAssembler::emit_i32_##name##i(Register dst, Register lhs, \
                                            int32_t imm) {              \
    instruction(dst, lhs, Operand(imm));                                \
  }

Definition at line 1079 of file liftoff-assembler-riscv64-inl.h.

I32_SHIFTOP

#define I32_SHIFTOP	(		name,
			instruction )

Value:

  void LiftoffAssembler::emit_i32_##name(Register dst, Register src, \
                                         Register amount) {          \
    instruction(dst, src, amount);                                   \
  }

Definition at line 1108 of file liftoff-assembler-riscv64-inl.h.

I32_SHIFTOP_I

#define I32_SHIFTOP_I	(		name,
			instruction )

Value:

  void LiftoffAssembler::emit_i32_##name##i(Register dst, Register src, \
                                            int amount) {               \
    instruction(dst, src, amount & 31);                                 \
  }

Definition at line 1113 of file liftoff-assembler-riscv64-inl.h.

I64_BINOP

#define I64_BINOP	(		name,
			instruction )

Value:

  void LiftoffAssembler::emit_i64_##name(                              \
      LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { \
    instruction(dst.gp(), lhs.gp(), rhs.gp());                         \
  }

Definition at line 1189 of file liftoff-assembler-riscv64-inl.h.

I64_BINOP_I

#define I64_BINOP_I	(		name,
			instruction )

Value:

  void LiftoffAssembler::emit_i64_##name##i(                   \
      LiftoffRegister dst, LiftoffRegister lhs, int32_t imm) { \
    instruction(dst.gp(), lhs.gp(), Operand(imm));             \
  }

Definition at line 1205 of file liftoff-assembler-riscv64-inl.h.

I64_SHIFTOP

#define I64_SHIFTOP	(		name,
			instruction )

Value:

  void LiftoffAssembler::emit_i64_##name(                          \
      LiftoffRegister dst, LiftoffRegister src, Register amount) { \
    instruction(dst.gp(), src.gp(), amount);                       \
  }

Definition at line 1219 of file liftoff-assembler-riscv64-inl.h.