 |
v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
|
|
v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
|
This is the complete list of members for v8::internal::AssemblerRISCVI, including all inherited members.
| add(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| addi(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| and_(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| andi(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| auipc(Register rd, int32_t imm20) | v8::internal::AssemblerRISCVI | |
| AuipcOffset(Instr instr) | v8::internal::AssemblerRISCVI | static |
| b(Label *L) | v8::internal::AssemblerRISCVI | inline |
| beq(Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| beq(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| beqz(Register rs, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| beqz(Register rs1, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bge(Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| bge(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bgeu(Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| bgeu(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bgez(Register rs, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| bgez(Register rs1, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bgt(Register rs1, Register rs2, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| bgt(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bgtu(Register rs1, Register rs2, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| bgtu(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bgtz(Register rs, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| bgtz(Register rs1, Label *L) | v8::internal::AssemblerRISCVI | inline |
| ble(Register rs1, Register rs2, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| ble(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bleu(Register rs1, Register rs2, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| bleu(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| blez(Register rs, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| blez(Register rs1, Label *L) | v8::internal::AssemblerRISCVI | inline |
| BlockTrampolinePoolFor(int instructions)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| blt(Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| blt(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bltu(Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| bltu(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bltz(Register rs, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| bltz(Register rs1, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bne(Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| bne(Register rs1, Register rs2, Label *L) | v8::internal::AssemblerRISCVI | inline |
| bnez(Register rs, int16_t imm13) | v8::internal::AssemblerRISCVI | inline |
| bnez(Register rs1, Label *L) | v8::internal::AssemblerRISCVI | inline |
| branch_offset(Label *L) | v8::internal::AssemblerRISCVI | inline |
| branch_offset_helper(Label *L, OffsetSize bits)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| call(int32_t offset) | v8::internal::AssemblerRISCVI | inline |
| ClearVectorunit()=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| ebreak() | v8::internal::AssemblerRISCVI | |
| ecall() | v8::internal::AssemblerRISCVI | |
| emit(Instr x)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| emit(ShortInstr x)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| emit(uint64_t x)=0 | v8::internal::AssemblerRiscvBase | protectedpure virtual |
| fence(uint8_t pred, uint8_t succ) | v8::internal::AssemblerRISCVI | |
| fence_tso() | v8::internal::AssemblerRISCVI | |
| GenInstrALU_ri(uint8_t funct3, Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALU_rr(uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, FPURegister rs1, FPURegister rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, FPURegister rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd, FPURegister rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd, FPURegister rs1, FPURegister rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrALUW_rr(uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrB(uint8_t funct3, BaseOpcode opcode, Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrBranchCC_rri(uint8_t funct3, Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCA(uint8_t funct6, BaseOpcode opcode, Register rd, uint8_t funct, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCB(uint8_t funct3, BaseOpcode opcode, Register rs1, uint8_t uimm8) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCBA(uint8_t funct3, uint8_t funct2, BaseOpcode opcode, Register rs1, int8_t imm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCI(uint8_t funct3, BaseOpcode opcode, Register rd, int8_t imm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCIU(uint8_t funct3, BaseOpcode opcode, Register rd, uint8_t uimm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCIU(uint8_t funct3, BaseOpcode opcode, FPURegister rd, uint8_t uimm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCIW(uint8_t funct3, BaseOpcode opcode, Register rd, uint8_t uimm8) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCJ(uint8_t funct3, BaseOpcode opcode, uint16_t uint11) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCL(uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t uimm5) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCL(uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, uint8_t uimm5) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCR(uint8_t funct4, BaseOpcode opcode, Register rd, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCS(uint8_t funct3, BaseOpcode opcode, Register rs2, Register rs1, uint8_t uimm5) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCS(uint8_t funct3, BaseOpcode opcode, FPURegister rs2, Register rs1, uint8_t uimm5) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCSR_ii(uint8_t funct3, Register rd, ControlStatusReg csr, uint8_t rs1) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCSR_ir(uint8_t funct3, Register rd, ControlStatusReg csr, Register rs1) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCSS(uint8_t funct3, BaseOpcode opcode, FPURegister rs2, uint8_t uimm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrCSS(uint8_t funct3, BaseOpcode opcode, Register rs2, uint8_t uimm6) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrI(uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrI(uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrIShift(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrIShiftW(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrJ(BaseOpcode opcode, Register rd, int32_t imm20) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrLoad_ri(uint8_t funct3, Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrLoadFP_ri(uint8_t funct3, FPURegister rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrPriv(uint8_t funct7, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, FPURegister rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, FPURegister rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR(uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, FPURegister rs1, FPURegister rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR4(uint8_t funct2, BaseOpcode opcode, Register rd, Register rs1, Register rs2, Register rs3, FPURoundingMode frm) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrR4(uint8_t funct2, BaseOpcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2, FPURegister rs3, FPURoundingMode frm) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrRAtomic(uint8_t funct5, bool aq, bool rl, uint8_t funct3, Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrRFrm(uint8_t funct7, BaseOpcode opcode, Register rd, Register rs1, Register rs2, FPURoundingMode frm) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrS(uint8_t funct3, BaseOpcode opcode, Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrS(uint8_t funct3, BaseOpcode opcode, Register rs1, FPURegister rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrShift_ri(bool arithshift, uint8_t funct3, Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrShiftW_ri(bool arithshift, uint8_t funct3, Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrStore_rri(uint8_t funct3, Register rs1, Register rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrStoreFP_rri(uint8_t funct3, Register rs1, FPURegister rs2, int16_t imm12) | v8::internal::AssemblerRiscvBase | protected |
| GenInstrU(BaseOpcode opcode, Register rd, int32_t imm20) | v8::internal::AssemblerRiscvBase | protected |
| IsAddi(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsAuipc(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsBranch(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsJal(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsJalr(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsJump(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsLui(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsLw(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsNop(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsOri(Instr instr) | v8::internal::AssemblerRISCVI | static |
| IsSlli(Instr instr) | v8::internal::AssemblerRISCVI | static |
| j(int32_t imm21) | v8::internal::AssemblerRISCVI | inline |
| j(Label *L) | v8::internal::AssemblerRISCVI | inline |
| jal(Register rd, int32_t imm20) | v8::internal::AssemblerRISCVI | |
| jal(int32_t imm21) | v8::internal::AssemblerRISCVI | inline |
| jal(Label *L) | v8::internal::AssemblerRISCVI | inline |
| jalr(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| jalr(Register rs, int32_t imm12) | v8::internal::AssemblerRISCVI | inline |
| jalr(Register rs) | v8::internal::AssemblerRISCVI | inline |
| JalrOffset(Instr instr) | v8::internal::AssemblerRISCVI | static |
| jr(Register rs) | v8::internal::AssemblerRISCVI | inline |
| jr(Register rs, int32_t imm12) | v8::internal::AssemblerRISCVI | inline |
| jump_offset(Label *L) | v8::internal::AssemblerRISCVI | inline |
| JumpOffset(Instr instr) | v8::internal::AssemblerRISCVI | static |
| kOffset11 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset12 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset13 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset20 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset21 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset32 enum value | v8::internal::AssemblerRiscvBase | protected |
| kOffset9 enum value | v8::internal::AssemblerRiscvBase | protected |
| lb(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| lbu(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| lh(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| lhu(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| LoadOffset(Instr instr) | v8::internal::AssemblerRISCVI | static |
| lui(Register rd, int32_t imm20) | v8::internal::AssemblerRISCVI | |
| lw(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| mv(Register rd, Register rs) | v8::internal::AssemblerRISCVI | inline |
| neg(Register rd, Register rs) | v8::internal::AssemblerRISCVI | inline |
| nor(Register rd, Register rs, Register rt) | v8::internal::AssemblerRISCVI | inline |
| not_(Register rd, Register rs) | v8::internal::AssemblerRISCVI | inline |
| OffsetSize enum name | v8::internal::AssemblerRiscvBase | protected |
| or_(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| ori(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| ret() | v8::internal::AssemblerRISCVI | inline |
| sb(Register source, Register base, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| seqz(Register rd, Register rs) | v8::internal::AssemblerRISCVI | inline |
| sgtz(Register rd, Register rs) | v8::internal::AssemblerRISCVI | inline |
| sh(Register source, Register base, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| sll(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| slli(Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRISCVI | |
| slt(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| slti(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| sltiu(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| sltu(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| sltz(Register rd, Register rs) | v8::internal::AssemblerRISCVI | inline |
| snez(Register rd, Register rs) | v8::internal::AssemblerRISCVI | inline |
| sra(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| srai(Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRISCVI | |
| srl(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| srli(Register rd, Register rs1, uint8_t shamt) | v8::internal::AssemblerRISCVI | |
| sub(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| sw(Register source, Register base, int16_t imm12) | v8::internal::AssemblerRISCVI | |
| sync() | v8::internal::AssemblerRISCVI | inline |
| unimp() | v8::internal::AssemblerRISCVI | |
| xor_(Register rd, Register rs1, Register rs2) | v8::internal::AssemblerRISCVI | |
| xori(Register rd, Register rs1, int16_t imm12) | v8::internal::AssemblerRISCVI |
1.12.0