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v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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#include <base-riscv-i.h>
Public Member Functions | |
| void | lui (Register rd, int32_t imm20) |
| void | auipc (Register rd, int32_t imm20) |
| void | jal (Register rd, int32_t imm20) |
| void | jalr (Register rd, Register rs1, int16_t imm12) |
| void | beq (Register rs1, Register rs2, int16_t imm12) |
| void | bne (Register rs1, Register rs2, int16_t imm12) |
| void | blt (Register rs1, Register rs2, int16_t imm12) |
| void | bge (Register rs1, Register rs2, int16_t imm12) |
| void | bltu (Register rs1, Register rs2, int16_t imm12) |
| void | bgeu (Register rs1, Register rs2, int16_t imm12) |
| void | lb (Register rd, Register rs1, int16_t imm12) |
| void | lh (Register rd, Register rs1, int16_t imm12) |
| void | lw (Register rd, Register rs1, int16_t imm12) |
| void | lbu (Register rd, Register rs1, int16_t imm12) |
| void | lhu (Register rd, Register rs1, int16_t imm12) |
| void | sb (Register source, Register base, int16_t imm12) |
| void | sh (Register source, Register base, int16_t imm12) |
| void | sw (Register source, Register base, int16_t imm12) |
| void | addi (Register rd, Register rs1, int16_t imm12) |
| void | slti (Register rd, Register rs1, int16_t imm12) |
| void | sltiu (Register rd, Register rs1, int16_t imm12) |
| void | xori (Register rd, Register rs1, int16_t imm12) |
| void | ori (Register rd, Register rs1, int16_t imm12) |
| void | andi (Register rd, Register rs1, int16_t imm12) |
| void | slli (Register rd, Register rs1, uint8_t shamt) |
| void | srli (Register rd, Register rs1, uint8_t shamt) |
| void | srai (Register rd, Register rs1, uint8_t shamt) |
| void | add (Register rd, Register rs1, Register rs2) |
| void | sub (Register rd, Register rs1, Register rs2) |
| void | sll (Register rd, Register rs1, Register rs2) |
| void | slt (Register rd, Register rs1, Register rs2) |
| void | sltu (Register rd, Register rs1, Register rs2) |
| void | xor_ (Register rd, Register rs1, Register rs2) |
| void | srl (Register rd, Register rs1, Register rs2) |
| void | sra (Register rd, Register rs1, Register rs2) |
| void | or_ (Register rd, Register rs1, Register rs2) |
| void | and_ (Register rd, Register rs1, Register rs2) |
| void | nor (Register rd, Register rs, Register rt) |
| void | fence (uint8_t pred, uint8_t succ) |
| void | fence_tso () |
| void | ecall () |
| void | ebreak () |
| void | sync () |
| void | unimp () |
| int32_t | branch_offset (Label *L) |
| int32_t | jump_offset (Label *L) |
| void | beq (Register rs1, Register rs2, Label *L) |
| void | bne (Register rs1, Register rs2, Label *L) |
| void | blt (Register rs1, Register rs2, Label *L) |
| void | bge (Register rs1, Register rs2, Label *L) |
| void | bltu (Register rs1, Register rs2, Label *L) |
| void | bgeu (Register rs1, Register rs2, Label *L) |
| void | beqz (Register rs, int16_t imm13) |
| void | beqz (Register rs1, Label *L) |
| void | bnez (Register rs, int16_t imm13) |
| void | bnez (Register rs1, Label *L) |
| void | blez (Register rs, int16_t imm13) |
| void | blez (Register rs1, Label *L) |
| void | bgez (Register rs, int16_t imm13) |
| void | bgez (Register rs1, Label *L) |
| void | bltz (Register rs, int16_t imm13) |
| void | bltz (Register rs1, Label *L) |
| void | bgtz (Register rs, int16_t imm13) |
| void | bgtz (Register rs1, Label *L) |
| void | bgt (Register rs1, Register rs2, int16_t imm13) |
| void | bgt (Register rs1, Register rs2, Label *L) |
| void | ble (Register rs1, Register rs2, int16_t imm13) |
| void | ble (Register rs1, Register rs2, Label *L) |
| void | bgtu (Register rs1, Register rs2, int16_t imm13) |
| void | bgtu (Register rs1, Register rs2, Label *L) |
| void | bleu (Register rs1, Register rs2, int16_t imm13) |
| void | bleu (Register rs1, Register rs2, Label *L) |
| void | j (int32_t imm21) |
| void | j (Label *L) |
| void | b (Label *L) |
| void | jal (int32_t imm21) |
| void | jal (Label *L) |
| void | jr (Register rs) |
| void | jr (Register rs, int32_t imm12) |
| void | jalr (Register rs, int32_t imm12) |
| void | jalr (Register rs) |
| void | ret () |
| void | call (int32_t offset) |
| void | mv (Register rd, Register rs) |
| void | not_ (Register rd, Register rs) |
| void | neg (Register rd, Register rs) |
| void | seqz (Register rd, Register rs) |
| void | snez (Register rd, Register rs) |
| void | sltz (Register rd, Register rs) |
| void | sgtz (Register rd, Register rs) |
Static Public Member Functions | |
| static int | JumpOffset (Instr instr) |
| static int | AuipcOffset (Instr instr) |
| static int | JalrOffset (Instr instr) |
| static int | LoadOffset (Instr instr) |
| static bool | IsBranch (Instr instr) |
| static bool | IsNop (Instr instr) |
| static bool | IsJump (Instr instr) |
| static bool | IsJal (Instr instr) |
| static bool | IsJalr (Instr instr) |
| static bool | IsLui (Instr instr) |
| static bool | IsAuipc (Instr instr) |
| static bool | IsAddi (Instr instr) |
| static bool | IsOri (Instr instr) |
| static bool | IsSlli (Instr instr) |
| static bool | IsLw (Instr instr) |
Additional Inherited Members | |
Protected Types inherited from v8::internal::AssemblerRiscvBase | |
| enum | OffsetSize : int { kOffset21 = 21 , kOffset12 = 12 , kOffset20 = 20 , kOffset13 = 13 , kOffset32 = 32 , kOffset11 = 11 , kOffset9 = 9 } |
Protected Member Functions inherited from v8::internal::AssemblerRiscvBase | |
| virtual int32_t | branch_offset_helper (Label *L, OffsetSize bits)=0 |
| virtual void | emit (Instr x)=0 |
| virtual void | emit (ShortInstr x)=0 |
| virtual void | emit (uint64_t x)=0 |
| virtual void | ClearVectorunit ()=0 |
| void | GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, Register rs2) |
| void | GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2) |
| void | GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, FPURegister rs1, Register rs2) |
| void | GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, Register rs2) |
| void | GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, FPURegister rs1, Register rs2) |
| void | GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, FPURegister rs1, FPURegister rs2) |
| void | GenInstrR4 (uint8_t funct2, BaseOpcode opcode, Register rd, Register rs1, Register rs2, Register rs3, FPURoundingMode frm) |
| void | GenInstrR4 (uint8_t funct2, BaseOpcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2, FPURegister rs3, FPURoundingMode frm) |
| void | GenInstrRAtomic (uint8_t funct5, bool aq, bool rl, uint8_t funct3, Register rd, Register rs1, Register rs2) |
| void | GenInstrRFrm (uint8_t funct7, BaseOpcode opcode, Register rd, Register rs1, Register rs2, FPURoundingMode frm) |
| void | GenInstrI (uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, int16_t imm12) |
| void | GenInstrI (uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, int16_t imm12) |
| void | GenInstrIShift (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t shamt) |
| void | GenInstrIShiftW (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t shamt) |
| void | GenInstrS (uint8_t funct3, BaseOpcode opcode, Register rs1, Register rs2, int16_t imm12) |
| void | GenInstrS (uint8_t funct3, BaseOpcode opcode, Register rs1, FPURegister rs2, int16_t imm12) |
| void | GenInstrB (uint8_t funct3, BaseOpcode opcode, Register rs1, Register rs2, int16_t imm12) |
| void | GenInstrU (BaseOpcode opcode, Register rd, int32_t imm20) |
| void | GenInstrJ (BaseOpcode opcode, Register rd, int32_t imm20) |
| void | GenInstrCR (uint8_t funct4, BaseOpcode opcode, Register rd, Register rs2) |
| void | GenInstrCA (uint8_t funct6, BaseOpcode opcode, Register rd, uint8_t funct, Register rs2) |
| void | GenInstrCI (uint8_t funct3, BaseOpcode opcode, Register rd, int8_t imm6) |
| void | GenInstrCIU (uint8_t funct3, BaseOpcode opcode, Register rd, uint8_t uimm6) |
| void | GenInstrCIU (uint8_t funct3, BaseOpcode opcode, FPURegister rd, uint8_t uimm6) |
| void | GenInstrCIW (uint8_t funct3, BaseOpcode opcode, Register rd, uint8_t uimm8) |
| void | GenInstrCSS (uint8_t funct3, BaseOpcode opcode, FPURegister rs2, uint8_t uimm6) |
| void | GenInstrCSS (uint8_t funct3, BaseOpcode opcode, Register rs2, uint8_t uimm6) |
| void | GenInstrCL (uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t uimm5) |
| void | GenInstrCL (uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, uint8_t uimm5) |
| void | GenInstrCS (uint8_t funct3, BaseOpcode opcode, Register rs2, Register rs1, uint8_t uimm5) |
| void | GenInstrCS (uint8_t funct3, BaseOpcode opcode, FPURegister rs2, Register rs1, uint8_t uimm5) |
| void | GenInstrCJ (uint8_t funct3, BaseOpcode opcode, uint16_t uint11) |
| void | GenInstrCB (uint8_t funct3, BaseOpcode opcode, Register rs1, uint8_t uimm8) |
| void | GenInstrCBA (uint8_t funct3, uint8_t funct2, BaseOpcode opcode, Register rs1, int8_t imm6) |
| void | GenInstrBranchCC_rri (uint8_t funct3, Register rs1, Register rs2, int16_t imm12) |
| void | GenInstrLoad_ri (uint8_t funct3, Register rd, Register rs1, int16_t imm12) |
| void | GenInstrStore_rri (uint8_t funct3, Register rs1, Register rs2, int16_t imm12) |
| void | GenInstrALU_ri (uint8_t funct3, Register rd, Register rs1, int16_t imm12) |
| void | GenInstrShift_ri (bool arithshift, uint8_t funct3, Register rd, Register rs1, uint8_t shamt) |
| void | GenInstrALU_rr (uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2) |
| void | GenInstrCSR_ir (uint8_t funct3, Register rd, ControlStatusReg csr, Register rs1) |
| void | GenInstrCSR_ii (uint8_t funct3, Register rd, ControlStatusReg csr, uint8_t rs1) |
| void | GenInstrShiftW_ri (bool arithshift, uint8_t funct3, Register rd, Register rs1, uint8_t shamt) |
| void | GenInstrALUW_rr (uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2) |
| void | GenInstrPriv (uint8_t funct7, Register rs1, Register rs2) |
| void | GenInstrLoadFP_ri (uint8_t funct3, FPURegister rd, Register rs1, int16_t imm12) |
| void | GenInstrStoreFP_rri (uint8_t funct3, Register rs1, FPURegister rs2, int16_t imm12) |
| void | GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, FPURegister rd, FPURegister rs1, FPURegister rs2) |
| void | GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, FPURegister rd, Register rs1, Register rs2) |
| void | GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, FPURegister rd, FPURegister rs1, Register rs2) |
| void | GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, Register rd, FPURegister rs1, Register rs2) |
| void | GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, Register rd, FPURegister rs1, FPURegister rs2) |
| virtual void | BlockTrampolinePoolFor (int instructions)=0 |
Definition at line 15 of file base-riscv-i.h.
Definition at line 101 of file base-riscv-i.cc.
| void v8::internal::AssemblerRISCVI::auipc | ( | Register | rd, |
| int32_t | imm20 ) |
Definition at line 13 of file base-riscv-i.cc.
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Definition at line 257 of file base-riscv-i.cc.
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Definition at line 135 of file base-riscv-i.h.
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Definition at line 105 of file base-riscv-i.h.
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| void v8::internal::AssemblerRISCVI::ebreak | ( | ) |
Definition at line 198 of file base-riscv-i.cc.
| void v8::internal::AssemblerRISCVI::ecall | ( | ) |
| void v8::internal::AssemblerRISCVI::fence | ( | uint8_t | pred, |
| uint8_t | succ ) |
Definition at line 181 of file base-riscv-i.cc.
| void v8::internal::AssemblerRISCVI::fence_tso | ( | ) |
Definition at line 209 of file base-riscv-i.cc.
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Definition at line 170 of file base-riscv-i.h.
| void v8::internal::AssemblerRISCVI::jal | ( | Register | rd, |
| int32_t | imm20 ) |
Definition at line 19 of file base-riscv-i.cc.
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Definition at line 174 of file base-riscv-i.h.
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Definition at line 251 of file base-riscv-i.cc.
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Definition at line 108 of file base-riscv-i.h.
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Definition at line 267 of file base-riscv-i.cc.
| void v8::internal::AssemblerRISCVI::lui | ( | Register | rd, |
| int32_t | imm20 ) |
Definition at line 181 of file base-riscv-i.h.
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| void v8::internal::AssemblerRISCVI::unimp | ( | ) |
Definition at line 113 of file base-riscv-i.cc.