v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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Public Member Functions | List of all members
v8::internal::AssemblerRISCVZicond Class Reference

#include <extension-riscv-zicond.h>

Inheritance diagram for v8::internal::AssemblerRISCVZicond:
Collaboration diagram for v8::internal::AssemblerRISCVZicond:

Public Member Functions

void czero_eqz (Register rd, Register rs1, Register rs2)
 
void czero_nez (Register rd, Register rs1, Register rs2)
 

Additional Inherited Members

- Protected Types inherited from v8::internal::AssemblerRiscvBase
enum  OffsetSize : int {
  kOffset21 = 21 , kOffset12 = 12 , kOffset20 = 20 , kOffset13 = 13 ,
  kOffset32 = 32 , kOffset11 = 11 , kOffset9 = 9
}
 
- Protected Member Functions inherited from v8::internal::AssemblerRiscvBase
virtual int32_t branch_offset_helper (Label *L, OffsetSize bits)=0
 
virtual void emit (Instr x)=0
 
virtual void emit (ShortInstr x)=0
 
virtual void emit (uint64_t x)=0
 
virtual void ClearVectorunit ()=0
 
void GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, Register rs2)
 
void GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2)
 
void GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, FPURegister rs1, Register rs2)
 
void GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, Register rs2)
 
void GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, FPURegister rd, FPURegister rs1, Register rs2)
 
void GenInstrR (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, FPURegister rs1, FPURegister rs2)
 
void GenInstrR4 (uint8_t funct2, BaseOpcode opcode, Register rd, Register rs1, Register rs2, Register rs3, FPURoundingMode frm)
 
void GenInstrR4 (uint8_t funct2, BaseOpcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2, FPURegister rs3, FPURoundingMode frm)
 
void GenInstrRAtomic (uint8_t funct5, bool aq, bool rl, uint8_t funct3, Register rd, Register rs1, Register rs2)
 
void GenInstrRFrm (uint8_t funct7, BaseOpcode opcode, Register rd, Register rs1, Register rs2, FPURoundingMode frm)
 
void GenInstrI (uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, int16_t imm12)
 
void GenInstrI (uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, int16_t imm12)
 
void GenInstrIShift (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t shamt)
 
void GenInstrIShiftW (uint8_t funct7, uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t shamt)
 
void GenInstrS (uint8_t funct3, BaseOpcode opcode, Register rs1, Register rs2, int16_t imm12)
 
void GenInstrS (uint8_t funct3, BaseOpcode opcode, Register rs1, FPURegister rs2, int16_t imm12)
 
void GenInstrB (uint8_t funct3, BaseOpcode opcode, Register rs1, Register rs2, int16_t imm12)
 
void GenInstrU (BaseOpcode opcode, Register rd, int32_t imm20)
 
void GenInstrJ (BaseOpcode opcode, Register rd, int32_t imm20)
 
void GenInstrCR (uint8_t funct4, BaseOpcode opcode, Register rd, Register rs2)
 
void GenInstrCA (uint8_t funct6, BaseOpcode opcode, Register rd, uint8_t funct, Register rs2)
 
void GenInstrCI (uint8_t funct3, BaseOpcode opcode, Register rd, int8_t imm6)
 
void GenInstrCIU (uint8_t funct3, BaseOpcode opcode, Register rd, uint8_t uimm6)
 
void GenInstrCIU (uint8_t funct3, BaseOpcode opcode, FPURegister rd, uint8_t uimm6)
 
void GenInstrCIW (uint8_t funct3, BaseOpcode opcode, Register rd, uint8_t uimm8)
 
void GenInstrCSS (uint8_t funct3, BaseOpcode opcode, FPURegister rs2, uint8_t uimm6)
 
void GenInstrCSS (uint8_t funct3, BaseOpcode opcode, Register rs2, uint8_t uimm6)
 
void GenInstrCL (uint8_t funct3, BaseOpcode opcode, Register rd, Register rs1, uint8_t uimm5)
 
void GenInstrCL (uint8_t funct3, BaseOpcode opcode, FPURegister rd, Register rs1, uint8_t uimm5)
 
void GenInstrCS (uint8_t funct3, BaseOpcode opcode, Register rs2, Register rs1, uint8_t uimm5)
 
void GenInstrCS (uint8_t funct3, BaseOpcode opcode, FPURegister rs2, Register rs1, uint8_t uimm5)
 
void GenInstrCJ (uint8_t funct3, BaseOpcode opcode, uint16_t uint11)
 
void GenInstrCB (uint8_t funct3, BaseOpcode opcode, Register rs1, uint8_t uimm8)
 
void GenInstrCBA (uint8_t funct3, uint8_t funct2, BaseOpcode opcode, Register rs1, int8_t imm6)
 
void GenInstrBranchCC_rri (uint8_t funct3, Register rs1, Register rs2, int16_t imm12)
 
void GenInstrLoad_ri (uint8_t funct3, Register rd, Register rs1, int16_t imm12)
 
void GenInstrStore_rri (uint8_t funct3, Register rs1, Register rs2, int16_t imm12)
 
void GenInstrALU_ri (uint8_t funct3, Register rd, Register rs1, int16_t imm12)
 
void GenInstrShift_ri (bool arithshift, uint8_t funct3, Register rd, Register rs1, uint8_t shamt)
 
void GenInstrALU_rr (uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2)
 
void GenInstrCSR_ir (uint8_t funct3, Register rd, ControlStatusReg csr, Register rs1)
 
void GenInstrCSR_ii (uint8_t funct3, Register rd, ControlStatusReg csr, uint8_t rs1)
 
void GenInstrShiftW_ri (bool arithshift, uint8_t funct3, Register rd, Register rs1, uint8_t shamt)
 
void GenInstrALUW_rr (uint8_t funct7, uint8_t funct3, Register rd, Register rs1, Register rs2)
 
void GenInstrPriv (uint8_t funct7, Register rs1, Register rs2)
 
void GenInstrLoadFP_ri (uint8_t funct3, FPURegister rd, Register rs1, int16_t imm12)
 
void GenInstrStoreFP_rri (uint8_t funct3, Register rs1, FPURegister rs2, int16_t imm12)
 
void GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, FPURegister rd, FPURegister rs1, FPURegister rs2)
 
void GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, FPURegister rd, Register rs1, Register rs2)
 
void GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, FPURegister rd, FPURegister rs1, Register rs2)
 
void GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, Register rd, FPURegister rs1, Register rs2)
 
void GenInstrALUFP_rr (uint8_t funct7, uint8_t funct3, Register rd, FPURegister rs1, FPURegister rs2)
 
virtual void BlockTrampolinePoolFor (int instructions)=0
 

Detailed Description

Definition at line 15 of file extension-riscv-zicond.h.

Member Function Documentation

◆ czero_eqz()

void v8::internal::AssemblerRISCVZicond::czero_eqz ( Register rd,
Register rs1,
Register rs2 )

Definition at line 15 of file extension-riscv-zicond.cc.

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◆ czero_nez()

void v8::internal::AssemblerRISCVZicond::czero_nez ( Register rd,
Register rs1,
Register rs2 )

Definition at line 19 of file extension-riscv-zicond.cc.

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The documentation for this class was generated from the following files: