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V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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code-generator-ia32.cc File Reference
#include "src/base/overflowing-math.h"
#include "src/codegen/assembler-inl.h"
#include "src/codegen/callable.h"
#include "src/codegen/cpu-features.h"
#include "src/codegen/ia32/assembler-ia32.h"
#include "src/codegen/ia32/register-ia32.h"
#include "src/codegen/interface-descriptors-inl.h"
#include "src/codegen/macro-assembler.h"
#include "src/codegen/optimized-compilation-info.h"
#include "src/compiler/backend/code-generator-impl.h"
#include "src/compiler/backend/code-generator.h"
#include "src/compiler/backend/gap-resolver.h"
#include "src/compiler/node-matchers.h"
#include "src/compiler/osr.h"
#include "src/execution/frame-constants.h"
#include "src/execution/frames.h"
#include "src/heap/mutable-page-metadata.h"
#include "src/objects/smi.h"
Include dependency graph for code-generator-ia32.cc:

Go to the source code of this file.

Classes

class  v8::internal::compiler::IA32OperandConverter
 

Namespaces

namespace  v8
 
namespace  v8::internal
 
namespace  v8::internal::compiler
 

Macros

#define __   masm()->
 
#define ASSEMBLE_COMPARE(asm_instr)
 
#define ASSEMBLE_IEEE754_BINOP(name)
 
#define ASSEMBLE_IEEE754_UNOP(name)
 
#define ASSEMBLE_BINOP(asm_instr)
 
#define ASSEMBLE_ATOMIC_BINOP(bin_inst, mov_inst, cmpxchg_inst)
 
#define ASSEMBLE_I64ATOMIC_BINOP(instr1, instr2)
 
#define ASSEMBLE_MOVX(mov_instr)
 
#define ASSEMBLE_SIMD_PUNPCK_SHUFFLE(opcode)
 
#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, SSELevel, imm)
 
#define ASSEMBLE_SIMD_ALL_TRUE(opcode)
 
#define ASSEMBLE_SIMD_SHIFT(opcode, width)
 
#define ASSEMBLE_SIMD_PINSR(OPCODE, CPU_FEATURE)
 
#define ATOMIC_BINOP_CASE(op, inst)
 
#define ATOMIC_BINOP_CASE(op, instr1, instr2)
 

Functions

static Condition v8::internal::compiler::FlagsConditionToCondition (FlagsCondition condition)
 

Macro Definition Documentation

◆ __

#define __   masm()->

Definition at line 33 of file code-generator-ia32.cc.

◆ ASSEMBLE_ATOMIC_BINOP

#define ASSEMBLE_ATOMIC_BINOP ( bin_inst,
mov_inst,
cmpxchg_inst )
Value:
do { \
Label binop; \
__ bind(&binop); \
__ mov_inst(eax, i.MemoryOperand(1)); \
__ Move(i.TempRegister(0), eax); \
__ bin_inst(i.TempRegister(0), i.InputRegister(0)); \
__ lock(); \
__ cmpxchg_inst(i.MemoryOperand(1), i.TempRegister(0)); \
__ j(not_equal, &binop); \
} while (false)
__
#define __
Definition code-generator-ia32.cc:33

Definition at line 422 of file code-generator-ia32.cc.

◆ ASSEMBLE_BINOP

#define ASSEMBLE_BINOP ( asm_instr)
Value:
do { \
if (HasAddressingMode(instr)) { \
size_t index = 1; \
Operand right = i.MemoryOperand(&index); \
__ asm_instr(i.InputRegister(0), right); \
} else { \
if (HasImmediateInput(instr, 1)) { \
__ asm_instr(i.InputOperand(0), i.InputImmediate(1)); \
} else { \
__ asm_instr(i.InputRegister(0), i.InputOperand(1)); \
} \
} \
} while (0)
instr
Instruction * instr
Definition jump-threading.cc:63

Definition at line 407 of file code-generator-ia32.cc.

◆ ASSEMBLE_COMPARE

#define ASSEMBLE_COMPARE ( asm_instr)
Value:
do { \
if (HasAddressingMode(instr)) { \
size_t index = 0; \
Operand left = i.MemoryOperand(&index); \
if (HasImmediateInput(instr, index)) { \
__ asm_instr(left, i.InputImmediate(index)); \
} else { \
__ asm_instr(left, i.InputRegister(index)); \
} \
} else { \
if (HasImmediateInput(instr, 1)) { \
if (HasRegisterInput(instr, 0)) { \
__ asm_instr(i.InputRegister(0), i.InputImmediate(1)); \
} else { \
__ asm_instr(i.InputOperand(0), i.InputImmediate(1)); \
} \
} else { \
if (HasRegisterInput(instr, 1)) { \
__ asm_instr(i.InputRegister(0), i.InputRegister(1)); \
} else { \
__ asm_instr(i.InputRegister(0), i.InputOperand(1)); \
} \
} \
} \
} while (0)

Definition at line 351 of file code-generator-ia32.cc.

◆ ASSEMBLE_I64ATOMIC_BINOP

#define ASSEMBLE_I64ATOMIC_BINOP ( instr1,
instr2 )
Value:
do { \
Label binop; \
__ bind(&binop); \
__ mov(eax, i.MemoryOperand(2)); \
__ mov(edx, i.NextMemoryOperand(2)); \
__ push(ebx); \
frame_access_state()->IncreaseSPDelta(1); \
i.MoveInstructionOperandToRegister(ebx, instr->InputAt(0)); \
__ push(i.InputRegister(1)); \
__ instr1(ebx, eax); \
__ instr2(i.InputRegister(1), edx); \
__ lock(); \
__ cmpxchg8b(i.MemoryOperand(2)); \
__ pop(i.InputRegister(1)); \
__ pop(ebx); \
frame_access_state()->IncreaseSPDelta(-1); \
__ j(not_equal, &binop); \
} while (false);

Definition at line 434 of file code-generator-ia32.cc.

◆ ASSEMBLE_IEEE754_BINOP

#define ASSEMBLE_IEEE754_BINOP ( name)
Value:
do { \
/* Pass two doubles as arguments on the stack. */ \
__ PrepareCallCFunction(4, eax); \
__ movsd(Operand(esp, 0 * kDoubleSize), i.InputDoubleRegister(0)); \
__ movsd(Operand(esp, 1 * kDoubleSize), i.InputDoubleRegister(1)); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 4); \
/* Return value is in st(0) on ia32. */ \
/* Store it into the result register. */ \
__ AllocateStackSpace(kDoubleSize); \
__ fstp_d(Operand(esp, 0)); \
__ movsd(i.OutputDoubleRegister(), Operand(esp, 0)); \
__ add(esp, Immediate(kDoubleSize)); \
} while (false)

Definition at line 378 of file code-generator-ia32.cc.

◆ ASSEMBLE_IEEE754_UNOP

#define ASSEMBLE_IEEE754_UNOP ( name)
Value:
do { \
/* Pass one double as argument on the stack. */ \
__ PrepareCallCFunction(2, eax); \
__ movsd(Operand(esp, 0 * kDoubleSize), i.InputDoubleRegister(0)); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 2); \
/* Return value is in st(0) on ia32. */ \
/* Store it into the result register. */ \
__ AllocateStackSpace(kDoubleSize); \
__ fstp_d(Operand(esp, 0)); \
__ movsd(i.OutputDoubleRegister(), Operand(esp, 0)); \
__ add(esp, Immediate(kDoubleSize)); \
} while (false)

Definition at line 393 of file code-generator-ia32.cc.

◆ ASSEMBLE_MOVX

#define ASSEMBLE_MOVX ( mov_instr)
Value:
do { \
if (HasAddressingMode(instr)) { \
__ mov_instr(i.OutputRegister(), i.MemoryOperand()); \
} else if (HasRegisterInput(instr, 0)) { \
__ mov_instr(i.OutputRegister(), i.InputRegister(0)); \
} else { \
__ mov_instr(i.OutputRegister(), i.InputOperand(0)); \
} \
} while (0)

Definition at line 454 of file code-generator-ia32.cc.

◆ ASSEMBLE_SIMD_ALL_TRUE

#define ASSEMBLE_SIMD_ALL_TRUE ( opcode)
Value:
do { \
Register dst = i.OutputRegister(); \
Operand src = i.InputOperand(0); \
Register tmp = i.TempRegister(0); \
XMMRegister tmp_simd = i.TempSimd128Register(1); \
__ mov(tmp, Immediate(1)); \
__ xor_(dst, dst); \
__ Pxor(tmp_simd, tmp_simd); \
__ opcode(tmp_simd, src); \
__ Ptest(tmp_simd, tmp_simd); \
__ cmov(zero, dst, tmp); \
} while (false)

Definition at line 489 of file code-generator-ia32.cc.

◆ ASSEMBLE_SIMD_IMM_SHUFFLE

#define ASSEMBLE_SIMD_IMM_SHUFFLE ( opcode,
SSELevel,
imm )
Value:
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
__ v##opcode(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputOperand(1), imm); \
} else { \
CpuFeatureScope sse_scope(masm(), SSELevel); \
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
__ opcode(i.OutputSimd128Register(), i.InputOperand(1), imm); \
}

Definition at line 478 of file code-generator-ia32.cc.

◆ ASSEMBLE_SIMD_PINSR

#define ASSEMBLE_SIMD_PINSR ( OPCODE,
CPU_FEATURE )
Value:
do { \
XMMRegister dst = i.OutputSimd128Register(); \
XMMRegister src = i.InputSimd128Register(0); \
int8_t laneidx = i.InputInt8(1); \
if (HasAddressingMode(instr)) { \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
__ v##OPCODE(dst, src, i.MemoryOperand(2), laneidx); \
} else { \
DCHECK_EQ(dst, src); \
CpuFeatureScope sse_scope(masm(), CPU_FEATURE); \
__ OPCODE(dst, i.MemoryOperand(2), laneidx); \
} \
} else { \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
__ v##OPCODE(dst, src, i.InputOperand(2), laneidx); \
} else { \
DCHECK_EQ(dst, src); \
CpuFeatureScope sse_scope(masm(), CPU_FEATURE); \
__ OPCODE(dst, i.InputOperand(2), laneidx); \
} \
} \
} while (false)

Definition at line 520 of file code-generator-ia32.cc.

◆ ASSEMBLE_SIMD_PUNPCK_SHUFFLE

#define ASSEMBLE_SIMD_PUNPCK_SHUFFLE ( opcode)
Value:
do { \
XMMRegister src0 = i.InputSimd128Register(0); \
Operand src1 = i.InputOperand(instr->InputCount() == 2 ? 1 : 0); \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
__ v##opcode(i.OutputSimd128Register(), src0, src1); \
} else { \
DCHECK_EQ(i.OutputSimd128Register(), src0); \
__ opcode(i.OutputSimd128Register(), src1); \
} \
} while (false)

Definition at line 465 of file code-generator-ia32.cc.

◆ ASSEMBLE_SIMD_SHIFT

#define ASSEMBLE_SIMD_SHIFT ( opcode,
width )
Value:
do { \
XMMRegister dst = i.OutputSimd128Register(); \
DCHECK_EQ(dst, i.InputSimd128Register(0)); \
if (HasImmediateInput(instr, 1)) { \
__ opcode(dst, dst, uint8_t{i.InputInt##width(1)}); \
} else { \
XMMRegister tmp = i.TempSimd128Register(0); \
Register tmp_shift = i.TempRegister(1); \
constexpr int mask = (1 << width) - 1; \
__ mov(tmp_shift, i.InputRegister(1)); \
__ and_(tmp_shift, Immediate(mask)); \
__ Movd(tmp, tmp_shift); \
__ opcode(dst, dst, tmp); \
} \
} while (false)
mask
uint32_t const mask
Definition machine-operator-reducer.cc:2278

Definition at line 503 of file code-generator-ia32.cc.

◆ ATOMIC_BINOP_CASE [1/2]

#define ATOMIC_BINOP_CASE ( op,
inst )
Value:
case kAtomic##op##Int8: { \
ASSEMBLE_ATOMIC_BINOP(inst, mov_b, cmpxchg_b); \
__ movsx_b(eax, eax); \
break; \
} \
case kAtomic##op##Uint8: { \
ASSEMBLE_ATOMIC_BINOP(inst, mov_b, cmpxchg_b); \
__ movzx_b(eax, eax); \
break; \
} \
case kAtomic##op##Int16: { \
ASSEMBLE_ATOMIC_BINOP(inst, mov_w, cmpxchg_w); \
__ movsx_w(eax, eax); \
break; \
} \
case kAtomic##op##Uint16: { \
ASSEMBLE_ATOMIC_BINOP(inst, mov_w, cmpxchg_w); \
__ movzx_w(eax, eax); \
break; \
} \
case kAtomic##op##Word32: { \
ASSEMBLE_ATOMIC_BINOP(inst, mov, cmpxchg); \
break; \
}
v8::internal::compiler::turboshaft::Word32
WordWithBits< 32 > Word32
Definition index.h:223

◆ ATOMIC_BINOP_CASE [2/2]

#define ATOMIC_BINOP_CASE ( op,
instr1,
instr2 )
Value:
case kIA32Word32AtomicPair##op: { \
DCHECK(VerifyOutputOfAtomicPairInstr(&i, instr)); \
ASSEMBLE_I64ATOMIC_BINOP(instr1, instr2) \
break; \
}

Variable Documentation

◆ input_

XMMRegister const input_
private

Definition at line 285 of file code-generator-ia32.cc.

◆ isolate_

Isolate* isolate_
private

Definition at line 289 of file code-generator-ia32.cc.

◆ mode_

RecordWriteMode const mode_
private

Definition at line 342 of file code-generator-ia32.cc.

◆ object_

Register const object_
private

Definition at line 337 of file code-generator-ia32.cc.

◆ operand_

Operand const operand_
private

Definition at line 338 of file code-generator-ia32.cc.

◆ result_

Register const result_
private

Definition at line 231 of file code-generator-ia32.cc.

◆ scratch0_

Register const scratch0_
private

Definition at line 340 of file code-generator-ia32.cc.

◆ scratch1_

Register const scratch1_
private

Definition at line 341 of file code-generator-ia32.cc.

◆ value_

Register const value_
private

Definition at line 339 of file code-generator-ia32.cc.

◆ zone_

Zone* zone_
private

Definition at line 290 of file code-generator-ia32.cc.