#include "src/codegen/assembler-inl.h"
#include "src/codegen/callable.h"
#include "src/codegen/interface-descriptors-inl.h"
#include "src/codegen/macro-assembler.h"
#include "src/codegen/optimized-compilation-info.h"
#include "src/codegen/riscv/constants-riscv.h"
#include "src/compiler/backend/code-generator-impl.h"
#include "src/compiler/backend/code-generator.h"
#include "src/compiler/backend/gap-resolver.h"
#include "src/compiler/node-matchers.h"
#include "src/compiler/osr.h"
#include "src/heap/mutable-page-metadata.h"

Include dependency graph for code-generator-riscv.cc:

Classes
class	v8::internal::compiler::RiscvOperandConverter

Namespaces
namespace	v8

namespace	v8::internal

namespace	v8::internal::compiler

Macros
#define	__ masm()->

#define	TRACE(...)

#define	ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr)

#define	ASSEMBLE_ATOMIC_STORE_INTEGER(asm_instr)

#define	ASSEMBLE_ATOMIC_BINOP(load_linked, store_conditional, bin_instr)

#define	ASSEMBLE_ATOMIC64_LOGIC_BINOP(bin_instr, external)

#define	ASSEMBLE_ATOMIC64_ARITH_BINOP(bin_instr, external)

#define	ASSEMBLE_ATOMIC_BINOP_EXT(load_linked, store_conditional, sign_extend, size, bin_instr, representation)

#define	ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(load_linked, store_conditional)

#define	ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT( load_linked, store_conditional, sign_extend, size, representation)

#define	ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(load_linked, store_conditional)

#define	ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT( load_linked, store_conditional, sign_extend, size, representation)

#define	ASSEMBLE_IEEE754_BINOP(name)

#define	ASSEMBLE_IEEE754_UNOP(name)

#define	ASSEMBLE_F64X2_ARITHMETIC_BINOP(op)

#define	ASSEMBLE_RVV_BINOP_INTEGER(instr, OP)

#define	ASSEMBLE_RVV_UNOP_INTEGER_VR(instr, OP)

#define	ASSEMBLE_RVV_UNOP_INTEGER_VV(instr, OP)

#define	UNSUPPORTED_COND(opcode, condition)

#define	__ masm->

#define	__ masm()->

Functions
static bool	v8::internal::compiler::HasRegisterInput (Instruction *instr, size_t index)

bool	v8::internal::compiler::IsInludeEqual (Condition cc)

void	v8::internal::compiler::AssembleBranchToLabels (CodeGenerator gen, MacroAssembler masm, Instruction instr, FlagsCondition condition, Label tlabel, Label *flabel, bool fallthru)

else	v8::internal::compiler::if (instr->arch_opcode()==kRiscvCmpZero)

	v8::internal::compiler::UNIMPLEMENTED ()

	v8::internal::compiler::if (!fallthru) __ Branch(flabel)

else	v8::internal::if (instr->arch_opcode()==kRiscvCmpZero)

	v8::internal::TRACE ("UNIMPLEMENTED code_generator_riscv64: %s at line %d\n", __FUNCTION__, __LINE__)

	v8::internal::UNIMPLEMENTED ()

Variables
	v8::internal::compiler::else

Macro Definition Documentation

◆ __ [1/3]

#define __ masm()->

Definition at line 27 of file code-generator-riscv.cc.

◆ __ [2/3]

#define __ masm->

Definition at line 27 of file code-generator-riscv.cc.

◆ __ [3/3]

#define __ masm()->

Definition at line 27 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC64_ARITH_BINOP

#define ASSEMBLE_ATOMIC64_ARITH_BINOP	(		bin_instr,
			external )

Value:

  do {                                                      \
    FrameScope scope(masm(), StackFrame::MANUAL);           \
    __ AddWord(a0, i.InputRegister(0), i.InputRegister(1)); \
    __ PushCallerSaved(SaveFPRegsMode::kIgnore, a0, a1);    \
    __ PrepareCallCFunction(3, 0, kScratchReg);             \
    __ CallCFunction(ExternalReference::external(), 3, 0);  \
    __ PopCallerSaved(SaveFPRegsMode::kIgnore, a0, a1);     \
  } while (0)

Definition at line 432 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC64_LOGIC_BINOP

#define ASSEMBLE_ATOMIC64_LOGIC_BINOP	(		bin_instr,
			external )

Value:

  do {                                                      \
    FrameScope scope(masm(), StackFrame::MANUAL);           \
    __ AddWord(a0, i.InputRegister(0), i.InputRegister(1)); \
    __ PushCallerSaved(SaveFPRegsMode::kIgnore, a0, a1);    \
    __ PrepareCallCFunction(3, 0, kScratchReg);             \
    __ CallCFunction(ExternalReference::external(), 3, 0);  \
    __ PopCallerSaved(SaveFPRegsMode::kIgnore, a0, a1);     \
  } while (0)

Definition at line 422 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC_BINOP

#define ASSEMBLE_ATOMIC_BINOP	(	load_linked,
		store_conditional,
		bin_instr )

Value:

  do {                                                                         \
    Label binop;                                                               \
    __ AddWord(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1));     \
    __ sync();                                                                 \
    __ bind(&binop);                                                           \
    __ load_linked(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0),      \
                   trapper);                                                   \
    __ bin_instr(i.TempRegister(1), i.OutputRegister(0),                       \
                 Operand(i.InputRegister(2)));                                 \
    __ store_conditional(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \
    __ BranchShort(&binop, ne, i.TempRegister(1), Operand(zero_reg));          \
    __ sync();                                                                 \
  } while (0)

Definition at line 407 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC_BINOP_EXT

#define ASSEMBLE_ATOMIC_BINOP_EXT	(	load_linked,
		store_conditional,
		sign_extend,
		size,
		bin_instr,
		representation )

Value:

  do {                                                                         \
    Label binop;                                                               \
    __ AddWord(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1));     \
    if (representation == 32) {                                                \
      __ And(i.TempRegister(3), i.TempRegister(0), 0x3);                       \
    } else {                                                                   \
      DCHECK_EQ(representation, 64);                                           \
      __ And(i.TempRegister(3), i.TempRegister(0), 0x7);                       \
    }                                                                          \
    __ SubWord(i.TempRegister(0), i.TempRegister(0),                           \
               Operand(i.TempRegister(3)));                                    \
    __ Sll32(i.TempRegister(3), i.TempRegister(3), 3);                         \
    __ sync();                                                                 \
    __ bind(&binop);                                                           \
    __ load_linked(i.TempRegister(1), MemOperand(i.TempRegister(0), 0),        \
                   trapper);                                                   \
    __ ExtractBits(i.OutputRegister(0), i.TempRegister(1), i.TempRegister(3),  \
                   size, sign_extend);                                         \
    __ bin_instr(i.TempRegister(2), i.OutputRegister(0),                       \
                 Operand(i.InputRegister(2)));                                 \
    __ InsertBits(i.TempRegister(1), i.TempRegister(2), i.TempRegister(3),     \
                  size);                                                       \
    __ store_conditional(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \
    __ BranchShort(&binop, ne, i.TempRegister(1), Operand(zero_reg));          \
    __ sync();                                                                 \
  } while (0)

Definition at line 442 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER

#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER	(		load_linked,
			store_conditional )

Value:

  do {                                                                         \
    Label compareExchange;                                                     \
    Label exit;                                                                \
    __ AddWord(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1));     \
    __ sync();                                                                 \
    __ bind(&compareExchange);                                                 \
    __ load_linked(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0),      \
                   trapper);                                                   \
    __ BranchShort(&exit, ne, i.InputRegister(2),                              \
                   Operand(i.OutputRegister(0)));                              \
    __ Move(i.TempRegister(2), i.InputRegister(3));                            \
    __ store_conditional(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \
    __ BranchShort(&compareExchange, ne, i.TempRegister(2),                    \
                   Operand(zero_reg));                                         \
    __ bind(&exit);                                                            \
    __ sync();                                                                 \
  } while (0)

Definition at line 512 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT

#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT	(	load_linked,
		store_conditional,
		sign_extend,
		size,
		representation )

Definition at line 532 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER

#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER	(		load_linked,
			store_conditional )

Value:

  do {                                                                         \
    Label exchange;                                                            \
    __ sync();                                                                 \
    __ bind(&exchange);                                                        \
    __ AddWord(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1));     \
    __ load_linked(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0),      \
                   trapper);                                                   \
    __ Move(i.TempRegister(1), i.InputRegister(2));                            \
    __ store_conditional(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \
    __ BranchShort(&exchange, ne, i.TempRegister(1), Operand(zero_reg));       \
    __ sync();                                                                 \
  } while (0)

Definition at line 471 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT

#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT	(	load_linked,
		store_conditional,
		sign_extend,
		size,
		representation )

Value:

  do {                                                                         \
    Label exchange;                                                            \
    __ AddWord(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1));     \
    if (representation == 32) {                                                \
      __ And(i.TempRegister(1), i.TempRegister(0), 0x3);                       \
    } else {                                                                   \
      DCHECK_EQ(representation, 64);                                           \
      __ And(i.TempRegister(1), i.TempRegister(0), 0x7);                       \
    }                                                                          \
    __ SubWord(i.TempRegister(0), i.TempRegister(0),                           \
               Operand(i.TempRegister(1)));                                    \
    __ Sll32(i.TempRegister(1), i.TempRegister(1), 3);                         \
    __ sync();                                                                 \
    __ bind(&exchange);                                                        \
    __ load_linked(i.TempRegister(2), MemOperand(i.TempRegister(0), 0),        \
                   trapper);                                                   \
    __ ExtractBits(i.OutputRegister(0), i.TempRegister(2), i.TempRegister(1),  \
                   size, sign_extend);                                         \
    __ InsertBits(i.TempRegister(2), i.InputRegister(2), i.TempRegister(1),    \
                  size);                                                       \
    __ store_conditional(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \
    __ BranchShort(&exchange, ne, i.TempRegister(2), Operand(zero_reg));       \
    __ sync();                                                                 \
  } while (0)

Definition at line 485 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC_LOAD_INTEGER

#define ASSEMBLE_ATOMIC_LOAD_INTEGER ( asm_instr )

Value:

  do {                                                            \
    __ asm_instr(i.OutputRegister(), i.MemoryOperand(), trapper); \
    __ sync();                                                    \
  } while (0)

Definition at line 394 of file code-generator-riscv.cc.

◆ ASSEMBLE_ATOMIC_STORE_INTEGER

#define ASSEMBLE_ATOMIC_STORE_INTEGER ( asm_instr )

Value:

  do {                                                                   \
    __ sync();                                                           \
    __ asm_instr(i.InputOrZeroRegister(0), i.MemoryOperand(1), trapper); \
    __ sync();                                                           \
  } while (0)

Definition at line 400 of file code-generator-riscv.cc.

◆ ASSEMBLE_F64X2_ARITHMETIC_BINOP

#define ASSEMBLE_F64X2_ARITHMETIC_BINOP ( op )

Value:

  do {                                                          \
    __ op(i.OutputSimd128Register(), i.InputSimd128Register(0), \
          i.InputSimd128Register(1));                           \
  } while (0)

Definition at line 587 of file code-generator-riscv.cc.

◆ ASSEMBLE_IEEE754_BINOP

#define ASSEMBLE_IEEE754_BINOP ( name )

Value:

  do {                                                                      \
    FrameScope scope(masm(), StackFrame::MANUAL);                           \
    __ PrepareCallCFunction(0, 2, kScratchReg);                             \
    __ MovToFloatParameters(i.InputDoubleRegister(0),                       \
                            i.InputDoubleRegister(1));                      \
    __ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 2); \
    /* Move the result in the double result register. */                    \
    __ MovFromFloatResult(i.OutputDoubleRegister());                        \
  } while (0)

Definition at line 566 of file code-generator-riscv.cc.

◆ ASSEMBLE_IEEE754_UNOP

#define ASSEMBLE_IEEE754_UNOP ( name )

Value:

  do {                                                                      \
    FrameScope scope(masm(), StackFrame::MANUAL);                           \
    __ PrepareCallCFunction(0, 1, kScratchReg);                             \
    __ MovToFloatParameter(i.InputDoubleRegister(0));                       \
    __ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 1); \
    /* Move the result in the double result register. */                    \
    __ MovFromFloatResult(i.OutputDoubleRegister());                        \
  } while (0)

Definition at line 577 of file code-generator-riscv.cc.

◆ ASSEMBLE_RVV_BINOP_INTEGER

#define ASSEMBLE_RVV_BINOP_INTEGER	(		instr,
			OP )

Value:

  case kRiscvI8x16##instr: {                                    \
    __ VU.set(kScratchReg, E8, m1);                             \
    __ OP(i.OutputSimd128Register(), i.InputSimd128Register(0), \
          i.InputSimd128Register(1));                           \
    break;                                                      \
  }                                                             \
  case kRiscvI16x8##instr: {                                    \
    __ VU.set(kScratchReg, E16, m1);                            \
    __ OP(i.OutputSimd128Register(), i.InputSimd128Register(0), \
          i.InputSimd128Register(1));                           \
    break;                                                      \
  }                                                             \
  case kRiscvI32x4##instr: {                                    \
    __ VU.set(kScratchReg, E32, m1);                            \
    __ OP(i.OutputSimd128Register(), i.InputSimd128Register(0), \
          i.InputSimd128Register(1));                           \
    break;                                                      \
  }

Definition at line 593 of file code-generator-riscv.cc.

◆ ASSEMBLE_RVV_UNOP_INTEGER_VR

#define ASSEMBLE_RVV_UNOP_INTEGER_VR	(		instr,
			OP )

Value:

  case kRiscvI8x16##instr: {                              \
    __ VU.set(kScratchReg, E8, m1);                       \
    __ OP(i.OutputSimd128Register(), i.InputRegister(0)); \
    break;                                                \
  }                                                       \
  case kRiscvI16x8##instr: {                              \
    __ VU.set(kScratchReg, E16, m1);                      \
    __ OP(i.OutputSimd128Register(), i.InputRegister(0)); \
    break;                                                \
  }                                                       \
  case kRiscvI32x4##instr: {                              \
    __ VU.set(kScratchReg, E32, m1);                      \
    __ OP(i.OutputSimd128Register(), i.InputRegister(0)); \
    break;                                                \
  }

Definition at line 613 of file code-generator-riscv.cc.

◆ ASSEMBLE_RVV_UNOP_INTEGER_VV

#define ASSEMBLE_RVV_UNOP_INTEGER_VV	(		instr,
			OP )

Value:

  case kRiscvI8x16##instr: {                                     \
    __ VU.set(kScratchReg, E8, m1);                              \
    __ OP(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
    break;                                                       \
  }                                                              \
  case kRiscvI16x8##instr: {                                     \
    __ VU.set(kScratchReg, E16, m1);                             \
    __ OP(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
    break;                                                       \
  }                                                              \
  case kRiscvI32x4##instr: {                                     \
    __ VU.set(kScratchReg, E32, m1);                             \
    __ OP(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
    break;                                                       \
  }                                                              \
  case kRiscvI64x2##instr: {                                     \
    __ VU.set(kScratchReg, E64, m1);                             \
    __ OP(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
    break;                                                       \
  }

Definition at line 630 of file code-generator-riscv.cc.

◆ TRACE

#define TRACE ( ... )

Value:

PrintF(__VA_ARGS__)

Definition at line 29 of file code-generator-riscv.cc.

◆ UNSUPPORTED_COND

#define UNSUPPORTED_COND	(		opcode,
			condition )

Value:

  StdoutStream{} << "Unsupported " << #opcode << " condition: \"" << condition \
                 << "\"";                                                      \
  UNIMPLEMENTED();

Definition at line 3807 of file code-generator-riscv.cc.

Variable Documentation

◆ indirect_pointer_tag_

IndirectPointerTag indirect_pointer_tag_

private

Definition at line 233 of file code-generator-riscv.cc.

◆ mode_

RecordWriteMode const mode_

private

Definition at line 227 of file code-generator-riscv.cc.

◆ must_save_lr_

bool must_save_lr_

private

Definition at line 231 of file code-generator-riscv.cc.

◆ object_

Register const object_

private

Definition at line 224 of file code-generator-riscv.cc.

◆ offset_

Operand const offset_

private

Definition at line 225 of file code-generator-riscv.cc.

◆ value_

Register const value_

private

Definition at line 226 of file code-generator-riscv.cc.

◆ zone_

Zone* zone_

private

Definition at line 232 of file code-generator-riscv.cc.

Classes

Namespaces

Macros

Functions

Variables

Macro Definition Documentation

◆ __ [1/3]

◆ __ [2/3]

◆ __ [3/3]

◆ ASSEMBLE_ATOMIC64_ARITH_BINOP

◆ ASSEMBLE_ATOMIC64_LOGIC_BINOP

◆ ASSEMBLE_ATOMIC_BINOP

◆ ASSEMBLE_ATOMIC_BINOP_EXT

◆ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER

◆ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT

◆ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER

◆ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT

◆ ASSEMBLE_ATOMIC_LOAD_INTEGER

◆ ASSEMBLE_ATOMIC_STORE_INTEGER

◆ ASSEMBLE_F64X2_ARITHMETIC_BINOP

◆ ASSEMBLE_IEEE754_BINOP

◆ ASSEMBLE_IEEE754_UNOP

◆ ASSEMBLE_RVV_BINOP_INTEGER

◆ ASSEMBLE_RVV_UNOP_INTEGER_VR

◆ ASSEMBLE_RVV_UNOP_INTEGER_VV

◆ TRACE

◆ UNSUPPORTED_COND

Variable Documentation

◆ indirect_pointer_tag_

◆ mode_

◆ must_save_lr_

◆ object_

◆ offset_

◆ value_

◆ zone_