v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
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code-generator-x64.cc File Reference
#include <limits>
#include <optional>
#include "src/base/logging.h"
#include "src/base/overflowing-math.h"
#include "src/builtins/builtins.h"
#include "src/codegen/assembler.h"
#include "src/codegen/cpu-features.h"
#include "src/codegen/external-reference.h"
#include "src/codegen/interface-descriptors-inl.h"
#include "src/codegen/macro-assembler.h"
#include "src/codegen/optimized-compilation-info.h"
#include "src/codegen/x64/assembler-x64.h"
#include "src/codegen/x64/register-x64.h"
#include "src/common/globals.h"
#include "src/common/ptr-compr-inl.h"
#include "src/compiler/backend/code-generator-impl.h"
#include "src/compiler/backend/code-generator.h"
#include "src/compiler/backend/gap-resolver.h"
#include "src/compiler/backend/instruction-codes.h"
#include "src/compiler/node-matchers.h"
#include "src/compiler/osr.h"
#include "src/execution/frame-constants.h"
#include "src/heap/heap-write-barrier.h"
#include "src/heap/mutable-page-metadata.h"
#include "src/objects/code-kind.h"
#include "src/objects/smi.h"
Include dependency graph for code-generator-x64.cc:

Go to the source code of this file.

Classes

class  v8::internal::compiler::X64OperandConverter
 

Namespaces

namespace  v8
 
namespace  v8::internal
 
namespace  v8::internal::compiler
 

Macros

#define __   masm()->
 
#define ASSEMBLE_UNOP(asm_instr)
 
#define ASSEMBLE_BINOP(asm_instr)
 
#define ASSEMBLE_COMPARE(cmp_instr, test_instr)
 
#define ASSEMBLE_TEST(asm_instr)
 
#define ASSEMBLE_MULT(asm_instr)
 
#define ASSEMBLE_SHIFT(asm_instr, width)
 
#define ASSEMBLE_MOVX(asm_instr)
 
#define ASSEMBLE_SSE_BINOP(asm_instr)
 
#define ASSEMBLE_SSE_UNOP(asm_instr)
 
#define ASSEMBLE_AVX_BINOP(asm_instr)
 
#define ASSEMBLE_IEEE754_BINOP(name)
 
#define ASSEMBLE_IEEE754_UNOP(name)
 
#define ASSEMBLE_ATOMIC_BINOP(bin_inst, mov_inst, cmpxchg_inst)
 
#define ASSEMBLE_ATOMIC64_BINOP(bin_inst, mov_inst, cmpxchg_inst)
 
#define ASSEMBLE_SIMD_BINOP(opcode)
 
#define ASSEMBLE_SIMD_F16x8_BINOP(instr)
 
#define ASSEMBLE_SIMD_F16x8_RELOP(instr)
 
#define ASSEMBLE_SIMD256_BINOP(opcode, cpu_feature)
 
#define ASSEMBLE_SIMD_INSTR(opcode, dst_operand, index)
 
#define ASSEMBLE_SIMD_IMM_INSTR(opcode, dst_operand, index, imm)
 
#define ASSEMBLE_SIMD_PUNPCK_SHUFFLE(opcode)
 
#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm)
 
#define ASSEMBLE_SIMD_ALL_TRUE(opcode)
 
#define ASSEMBLE_SIMD_SHIFT(opcode, width)
 
#define ASSEMBLE_SIMD256_SHIFT(opcode, width)
 
#define ASSEMBLE_PINSR(ASM_INSTR)
 
#define ASSEMBLE_SEQ_CST_STORE(rep)
 
#define ATOMIC_BINOP_CASE(op, inst32, inst64)
 

Enumerations

enum class  v8::internal::compiler::FirstMacroFusionInstKind {
  v8::internal::compiler::kTest , v8::internal::compiler::kCmp , v8::internal::compiler::kAnd , v8::internal::compiler::kAddSub ,
  v8::internal::compiler::kIncDec , v8::internal::compiler::kInvalid
}
 
enum class  v8::internal::compiler::SecondMacroFusionInstKind { v8::internal::compiler::kAB , v8::internal::compiler::kELG , v8::internal::compiler::kInvalid }
 

Functions

bool v8::internal::compiler::IsMacroFused (FirstMacroFusionInstKind first_kind, SecondMacroFusionInstKind second_kind)
 
SecondMacroFusionInstKind v8::internal::compiler::GetSecondMacroFusionInstKind (FlagsCondition condition)
 
bool v8::internal::compiler::ShouldAlignForJCCErratum (Instruction *instr, FirstMacroFusionInstKind first_kind)
 
bool v8::internal::compiler::ShouldClearOutputRegisterBeforeInstruction (CodeGenerator *g, Instruction *instr)
 

Macro Definition Documentation

◆ __

#define __   masm()->

Definition at line 40 of file code-generator-x64.cc.

◆ ASSEMBLE_ATOMIC64_BINOP

#define ASSEMBLE_ATOMIC64_BINOP ( bin_inst,
mov_inst,
cmpxchg_inst )
Value:
do { \
Label binop; \
__ bind(&binop); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ mov_inst(rax, i.MemoryOperand(1)); \
__ movq(i.TempRegister(0), rax); \
__ bin_inst(i.TempRegister(0), i.InputRegister(0)); \
__ lock(); \
__ cmpxchg_inst(i.MemoryOperand(1), i.TempRegister(0)); \
__ j(not_equal, &binop); \
} while (false)
__
#define __
Definition code-generator-x64.cc:40
instr
Instruction * instr
Definition jump-threading.cc:63
pc_offset
int pc_offset
Definition liftoff-compiler.cc:9470

Definition at line 1092 of file code-generator-x64.cc.

◆ ASSEMBLE_ATOMIC_BINOP

#define ASSEMBLE_ATOMIC_BINOP ( bin_inst,
mov_inst,
cmpxchg_inst )
Value:
do { \
Label binop; \
__ bind(&binop); \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, __ pc_offset()); \
__ mov_inst(rax, i.MemoryOperand(1)); \
__ movl(i.TempRegister(0), rax); \
__ bin_inst(i.TempRegister(0), i.InputRegister(0)); \
__ lock(); \
__ cmpxchg_inst(i.MemoryOperand(1), i.TempRegister(0)); \
__ j(not_equal, &binop); \
} while (false)

Definition at line 1079 of file code-generator-x64.cc.

◆ ASSEMBLE_AVX_BINOP

#define ASSEMBLE_AVX_BINOP ( asm_instr)
Value:
do { \
CpuFeatureScope avx_scope(masm(), AVX); \
if (HasAddressingMode(instr)) { \
size_t index = 1; \
Operand right = i.MemoryOperand(&index); \
__ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), right); \
} else { \
if (instr->InputAt(1)->IsFPRegister()) { \
__ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), \
i.InputDoubleRegister(1)); \
} else { \
__ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), \
i.InputOperand(1)); \
} \
} \
} while (false)

Definition at line 1049 of file code-generator-x64.cc.

◆ ASSEMBLE_BINOP

#define ASSEMBLE_BINOP ( asm_instr)
Value:
do { \
if (HasAddressingMode(instr)) { \
size_t index = 1; \
Operand right = i.MemoryOperand(&index); \
__ asm_instr(i.InputRegister(0), right); \
} else { \
if (HasImmediateInput(instr, 1)) { \
if (HasRegisterInput(instr, 0)) { \
__ asm_instr(i.InputRegister(0), i.InputImmediate(1)); \
} else { \
__ asm_instr(i.InputOperand(0), i.InputImmediate(1)); \
} \
} else { \
if (HasRegisterInput(instr, 1)) { \
__ asm_instr(i.InputRegister(0), i.InputRegister(1)); \
} else { \
__ asm_instr(i.InputRegister(0), i.InputOperand(1)); \
} \
} \
} \
} while (false)

Definition at line 896 of file code-generator-x64.cc.

◆ ASSEMBLE_COMPARE

#define ASSEMBLE_COMPARE ( cmp_instr,
test_instr )
Value:
do { \
if (HasAddressingMode(instr)) { \
size_t index = 0; \
Operand left = i.MemoryOperand(&index); \
if (HasImmediateInput(instr, index)) { \
__ cmp_instr(left, i.InputImmediate(index)); \
} else { \
__ cmp_instr(left, i.InputRegister(index)); \
} \
} else { \
if (HasImmediateInput(instr, 1)) { \
Immediate right = i.InputImmediate(1); \
if (HasRegisterInput(instr, 0)) { \
if (right.value() == 0) { \
__ test_instr(i.InputRegister(0), i.InputRegister(0)); \
} else { \
__ cmp_instr(i.InputRegister(0), right); \
} \
} else { \
__ cmp_instr(i.InputOperand(0), right); \
} \
} else { \
if (HasRegisterInput(instr, 1)) { \
__ cmp_instr(i.InputRegister(0), i.InputRegister(1)); \
} else { \
__ cmp_instr(i.InputRegister(0), i.InputOperand(1)); \
} \
} \
} \
} while (false)

Definition at line 919 of file code-generator-x64.cc.

◆ ASSEMBLE_IEEE754_BINOP

#define ASSEMBLE_IEEE754_BINOP ( name)
Value:
do { \
__ PrepareCallCFunction(2); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 2); \
} while (false)

Definition at line 1067 of file code-generator-x64.cc.

◆ ASSEMBLE_IEEE754_UNOP

#define ASSEMBLE_IEEE754_UNOP ( name)
Value:
do { \
__ PrepareCallCFunction(1); \
__ CallCFunction(ExternalReference::ieee754_##name##_function(), 1); \
} while (false)

Definition at line 1073 of file code-generator-x64.cc.

◆ ASSEMBLE_MOVX

#define ASSEMBLE_MOVX ( asm_instr)
Value:
do { \
if (HasAddressingMode(instr)) { \
__ asm_instr(i.OutputRegister(), i.MemoryOperand()); \
} else if (HasRegisterInput(instr, 0)) { \
__ asm_instr(i.OutputRegister(), i.InputRegister(0)); \
} else { \
__ asm_instr(i.OutputRegister(), i.InputOperand(0)); \
} \
} while (false)

Definition at line 1014 of file code-generator-x64.cc.

◆ ASSEMBLE_MULT

#define ASSEMBLE_MULT ( asm_instr)
Value:
do { \
if (HasImmediateInput(instr, 1)) { \
if (HasRegisterInput(instr, 0)) { \
__ asm_instr(i.OutputRegister(), i.InputRegister(0), \
i.InputImmediate(1)); \
} else { \
__ asm_instr(i.OutputRegister(), i.InputOperand(0), \
i.InputImmediate(1)); \
} \
} else { \
if (HasRegisterInput(instr, 1)) { \
__ asm_instr(i.OutputRegister(), i.InputRegister(1)); \
} else { \
__ asm_instr(i.OutputRegister(), i.InputOperand(1)); \
} \
} \
} while (false)

Definition at line 978 of file code-generator-x64.cc.

◆ ASSEMBLE_PINSR

#define ASSEMBLE_PINSR ( ASM_INSTR)
Value:
do { \
XMMRegister dst = i.OutputSimd128Register(); \
XMMRegister src = i.InputSimd128Register(0); \
uint8_t laneidx = i.InputUint8(1); \
uint32_t load_offset; \
if (HasAddressingMode(instr)) { \
__ ASM_INSTR(dst, src, i.MemoryOperand(2), laneidx, &load_offset); \
} else if (instr->InputAt(2)->IsFPRegister()) { \
__ Movq(kScratchRegister, i.InputDoubleRegister(2)); \
__ ASM_INSTR(dst, src, kScratchRegister, laneidx, &load_offset); \
} else if (instr->InputAt(2)->IsRegister()) { \
__ ASM_INSTR(dst, src, i.InputRegister(2), laneidx, &load_offset); \
} else { \
__ ASM_INSTR(dst, src, i.InputOperand(2), laneidx, &load_offset); \
} \
RecordTrapInfoIfNeeded(zone(), this, opcode, instr, load_offset); \
} while (false)

Definition at line 1258 of file code-generator-x64.cc.

◆ ASSEMBLE_SEQ_CST_STORE

#define ASSEMBLE_SEQ_CST_STORE ( rep)
Value:
do { \
Register value = i.InputRegister(0); \
Operand operand = i.MemoryOperand(1); \
EmitTSANAwareStore<std::memory_order_seq_cst>( \
zone(), this, masm(), operand, value, i, DetermineStubCallMode(), rep, \
instr); \
} while (false)

Definition at line 1277 of file code-generator-x64.cc.

◆ ASSEMBLE_SHIFT

#define ASSEMBLE_SHIFT ( asm_instr,
width )
Value:
do { \
if (HasImmediateInput(instr, 1)) { \
if (instr->Output()->IsRegister()) { \
__ asm_instr(i.OutputRegister(), Immediate(i.InputInt##width(1))); \
} else { \
__ asm_instr(i.OutputOperand(), Immediate(i.InputInt##width(1))); \
} \
} else { \
if (instr->Output()->IsRegister()) { \
__ asm_instr##_cl(i.OutputRegister()); \
} else { \
__ asm_instr##_cl(i.OutputOperand()); \
} \
} \
} while (false)

Definition at line 997 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD256_BINOP

#define ASSEMBLE_SIMD256_BINOP ( opcode,
cpu_feature )
Value:
do { \
CpuFeatureScope avx_scope(masm(), cpu_feature); \
__ v##opcode(i.OutputSimd256Register(), i.InputSimd256Register(0), \
i.InputSimd256Register(1)); \
} while (false)

Definition at line 1144 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD256_SHIFT

#define ASSEMBLE_SIMD256_SHIFT ( opcode,
width )
Value:
do { \
CpuFeatureScope avx_scope(masm(), AVX2); \
YMMRegister src = i.InputSimd256Register(0); \
YMMRegister dst = i.OutputSimd256Register(); \
if (HasImmediateInput(instr, 1)) { \
__ v##opcode(dst, src, uint8_t{i.InputInt##width(1)}); \
} else { \
constexpr int mask = (1 << width) - 1; \
__ movq(kScratchRegister, i.InputRegister(1)); \
__ andq(kScratchRegister, Immediate(mask)); \
__ Movq(kScratchDoubleReg, kScratchRegister); \
__ v##opcode(dst, src, kScratchDoubleReg); \
} \
} while (false)
mask
uint32_t const mask
Definition machine-operator-reducer.cc:2278

Definition at line 1242 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_ALL_TRUE

#define ASSEMBLE_SIMD_ALL_TRUE ( opcode)
Value:
do { \
Register dst = i.OutputRegister(); \
__ xorq(dst, dst); \
__ Pxor(kScratchDoubleReg, kScratchDoubleReg); \
__ opcode(kScratchDoubleReg, i.InputSimd128Register(0)); \
__ Ptest(kScratchDoubleReg, kScratchDoubleReg); \
__ setcc(equal, dst); \
} while (false)

Definition at line 1202 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_BINOP

#define ASSEMBLE_SIMD_BINOP ( opcode)
Value:
do { \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
__ v##opcode(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1)); \
} else { \
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
__ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1)); \
} \
} while (false)

Definition at line 1108 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_F16x8_BINOP

#define ASSEMBLE_SIMD_F16x8_BINOP ( instr)
Value:
do { \
CpuFeatureScope f16c_scope(masm(), F16C); \
CpuFeatureScope avx_scope(masm(), AVX); \
YMMRegister tmp1 = i.TempSimd256Register(0); \
YMMRegister tmp2 = i.TempSimd256Register(1); \
__ vcvtph2ps(tmp1, i.InputSimd128Register(0)); \
__ vcvtph2ps(tmp2, i.InputSimd128Register(1)); \
__ instr(tmp2, tmp1, tmp2); \
__ vcvtps2ph(i.OutputSimd128Register(), tmp2, 0); \
} while (false)

Definition at line 1120 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_F16x8_RELOP

#define ASSEMBLE_SIMD_F16x8_RELOP ( instr)
Value:
do { \
CpuFeatureScope f16c_scope(masm(), F16C); \
CpuFeatureScope avx_scope(masm(), AVX); \
YMMRegister tmp1 = i.TempSimd256Register(0); \
YMMRegister tmp2 = i.TempSimd256Register(1); \
__ vcvtph2ps(tmp1, i.InputSimd128Register(0)); \
__ vcvtph2ps(tmp2, i.InputSimd128Register(1)); \
__ instr(tmp2, tmp1, tmp2); \
__ vpackssdw(i.OutputSimd128Register(), tmp2, tmp2); \
} while (false)

Definition at line 1132 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_IMM_INSTR

#define ASSEMBLE_SIMD_IMM_INSTR ( opcode,
dst_operand,
index,
imm )
Value:
do { \
if (instr->InputAt(index)->IsSimd128Register()) { \
__ opcode(dst_operand, i.InputSimd128Register(index), imm); \
} else { \
__ opcode(dst_operand, i.InputOperand(index), imm); \
} \
} while (false)

Definition at line 1160 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_IMM_SHUFFLE

#define ASSEMBLE_SIMD_IMM_SHUFFLE ( opcode,
imm )
Value:
do { \
XMMRegister dst = i.OutputSimd128Register(); \
XMMRegister src = i.InputSimd128Register(0); \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
DCHECK(instr->InputAt(1)->IsSimd128Register()); \
__ v##opcode(dst, src, i.InputSimd128Register(1), imm); \
} else { \
DCHECK_EQ(dst, src); \
if (instr->InputAt(1)->IsSimd128Register()) { \
__ opcode(dst, i.InputSimd128Register(1), imm); \
} else { \
__ opcode(dst, i.InputOperand(1), imm); \
} \
} \
} while (false)

Definition at line 1184 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_INSTR

#define ASSEMBLE_SIMD_INSTR ( opcode,
dst_operand,
index )
Value:
do { \
if (instr->InputAt(index)->IsSimd128Register()) { \
__ opcode(dst_operand, i.InputSimd128Register(index)); \
} else { \
__ opcode(dst_operand, i.InputOperand(index)); \
} \
} while (false)

Definition at line 1151 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_PUNPCK_SHUFFLE

#define ASSEMBLE_SIMD_PUNPCK_SHUFFLE ( opcode)
Value:
do { \
XMMRegister dst = i.OutputSimd128Register(); \
uint8_t input_index = instr->InputCount() == 2 ? 1 : 0; \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
DCHECK(instr->InputAt(input_index)->IsSimd128Register()); \
__ v##opcode(dst, i.InputSimd128Register(0), \
i.InputSimd128Register(input_index)); \
} else { \
DCHECK_EQ(dst, i.InputSimd128Register(0)); \
ASSEMBLE_SIMD_INSTR(opcode, dst, input_index); \
} \
} while (false)

Definition at line 1169 of file code-generator-x64.cc.

◆ ASSEMBLE_SIMD_SHIFT

#define ASSEMBLE_SIMD_SHIFT ( opcode,
width )
Value:
do { \
XMMRegister dst = i.OutputSimd128Register(); \
if (HasImmediateInput(instr, 1)) { \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
__ v##opcode(dst, i.InputSimd128Register(0), \
uint8_t{i.InputInt##width(1)}); \
} else { \
DCHECK_EQ(dst, i.InputSimd128Register(0)); \
__ opcode(dst, uint8_t{i.InputInt##width(1)}); \
} \
} else { \
constexpr int mask = (1 << width) - 1; \
__ movq(kScratchRegister, i.InputRegister(1)); \
__ andq(kScratchRegister, Immediate(mask)); \
__ Movq(kScratchDoubleReg, kScratchRegister); \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope avx_scope(masm(), AVX); \
__ v##opcode(dst, i.InputSimd128Register(0), kScratchDoubleReg); \
} else { \
DCHECK_EQ(dst, i.InputSimd128Register(0)); \
__ opcode(dst, kScratchDoubleReg); \
} \
} \
} while (false)

Definition at line 1215 of file code-generator-x64.cc.

◆ ASSEMBLE_SSE_BINOP

#define ASSEMBLE_SSE_BINOP ( asm_instr)
Value:
do { \
if (HasAddressingMode(instr)) { \
size_t index = 1; \
Operand right = i.MemoryOperand(&index); \
__ asm_instr(i.InputDoubleRegister(0), right); \
} else { \
if (instr->InputAt(1)->IsFPRegister()) { \
__ asm_instr(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); \
} else { \
__ asm_instr(i.InputDoubleRegister(0), i.InputOperand(1)); \
} \
} \
} while (false)

Definition at line 1025 of file code-generator-x64.cc.

◆ ASSEMBLE_SSE_UNOP

#define ASSEMBLE_SSE_UNOP ( asm_instr)
Value:
do { \
if (instr->InputAt(0)->IsFPRegister()) { \
__ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); \
} else { \
__ asm_instr(i.OutputDoubleRegister(), i.InputOperand(0)); \
} \
} while (false)

Definition at line 1040 of file code-generator-x64.cc.

◆ ASSEMBLE_TEST

#define ASSEMBLE_TEST ( asm_instr)
Value:
do { \
if (HasAddressingMode(instr)) { \
size_t index = 0; \
Operand left = i.MemoryOperand(&index); \
if (HasImmediateInput(instr, index)) { \
__ asm_instr(left, i.InputImmediate(index)); \
} else { \
__ asm_instr(left, i.InputRegister(index)); \
} \
} else { \
if (HasImmediateInput(instr, 1)) { \
if (HasRegisterInput(instr, 0)) { \
__ asm_instr(i.InputRegister(0), i.InputImmediate(1)); \
} else { \
__ asm_instr(i.InputOperand(0), i.InputImmediate(1)); \
} \
} else { \
if (HasRegisterInput(instr, 1)) { \
__ asm_instr(i.InputRegister(0), i.InputRegister(1)); \
} else { \
__ asm_instr(i.InputRegister(0), i.InputOperand(1)); \
} \
} \
} \
} while (false)

Definition at line 951 of file code-generator-x64.cc.

◆ ASSEMBLE_UNOP

#define ASSEMBLE_UNOP ( asm_instr)
Value:
do { \
if (instr->Output()->IsRegister()) { \
__ asm_instr(i.OutputRegister()); \
} else { \
__ asm_instr(i.OutputOperand()); \
} \
} while (false)

Definition at line 887 of file code-generator-x64.cc.

◆ ATOMIC_BINOP_CASE

#define ATOMIC_BINOP_CASE ( op,
inst32,
inst64 )

Variable Documentation

◆ indirect_pointer_tag_

IndirectPointerTag indirect_pointer_tag_
private

Definition at line 467 of file code-generator-x64.cc.

◆ input_

XMMRegister const input_
private

Definition at line 360 of file code-generator-x64.cc.

◆ isolate_

Isolate* isolate_
private

Definition at line 365 of file code-generator-x64.cc.

◆ mode_

RecordWriteMode const mode_
private

Definition at line 462 of file code-generator-x64.cc.

◆ object_

Register const object_
private

Definition at line 457 of file code-generator-x64.cc.

◆ operand_

Operand const operand_
private

Definition at line 458 of file code-generator-x64.cc.

◆ result_

Register const result_
private

Definition at line 298 of file code-generator-x64.cc.

◆ scratch0_

Register const scratch0_
private

Definition at line 460 of file code-generator-x64.cc.

◆ scratch1_

Register const scratch1_
private

Definition at line 461 of file code-generator-x64.cc.

◆ unwinding_info_writer_

UnwindingInfoWriter* const unwinding_info_writer_
private

Definition at line 364 of file code-generator-x64.cc.

◆ value_

Register const value_
private

Definition at line 459 of file code-generator-x64.cc.

◆ zone_

Zone* zone_
private

Definition at line 366 of file code-generator-x64.cc.