v8
V8 is Google’s open source high-performance JavaScript and WebAssembly engine, written in C++.
Loading...
Searching...
No Matches
extension-riscv-v.cc File Reference
Include dependency graph for extension-riscv-v.cc:

Go to the source code of this file.

Namespaces

namespace  v8
 
namespace  v8::internal
 

Macros

#define DEFINE_OPIVV(name, funct6)
 
#define DEFINE_OPFVV(name, funct6)
 
#define DEFINE_OPFWV(name, funct6)
 
#define DEFINE_OPFRED(name, funct6)
 
#define DEFINE_OPIVX(name, funct6)
 
#define DEFINE_OPIVI(name, funct6)
 
#define DEFINE_OPMVV(name, funct6)
 
#define DEFINE_OPMVX(name, funct6)
 
#define DEFINE_OPFVF(name, funct6)
 
#define DEFINE_OPFWF(name, funct6)
 
#define DEFINE_OPFVV_FMA(name, funct6)
 
#define DEFINE_OPFVF_FMA(name, funct6)
 
#define DEFINE_OPMVV_VIE(name, vs1)
 

Functions

uint8_t v8::internal::vsew_switch (VSew vsew)
 

Macro Definition Documentation

◆ DEFINE_OPFRED

#define DEFINE_OPFRED ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vs(VRegister vd, VRegister vs2, VRegister vs1, \
MaskType mask) { \
GenInstrV(funct6, OP_FVV, vd, vs1, vs2, mask); \
}
uint32_t const mask

Definition at line 139 of file extension-riscv-v.cc.

◆ DEFINE_OPFVF

#define DEFINE_OPFVF ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vf(VRegister vd, VRegister vs2, \
FPURegister fs1, MaskType mask) { \
GenInstrV(funct6, OP_FVF, vd, fs1, vs2, mask); \
}

Definition at line 172 of file extension-riscv-v.cc.

◆ DEFINE_OPFVF_FMA

#define DEFINE_OPFVF_FMA ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vf(VRegister vd, FPURegister fs1, \
VRegister vs2, MaskType mask) { \
GenInstrV(funct6, OP_FVF, vd, fs1, vs2, mask); \
}

Definition at line 190 of file extension-riscv-v.cc.

◆ DEFINE_OPFVV

#define DEFINE_OPFVV ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vv(VRegister vd, VRegister vs2, VRegister vs1, \
MaskType mask) { \
GenInstrV(funct6, OP_FVV, vd, vs1, vs2, mask); \
}

Definition at line 127 of file extension-riscv-v.cc.

◆ DEFINE_OPFVV_FMA

#define DEFINE_OPFVV_FMA ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vv(VRegister vd, VRegister vs1, VRegister vs2, \
MaskType mask) { \
GenInstrV(funct6, OP_FVV, vd, vs1, vs2, mask); \
}

Definition at line 184 of file extension-riscv-v.cc.

◆ DEFINE_OPFWF

#define DEFINE_OPFWF ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_wf(VRegister vd, VRegister vs2, \
FPURegister fs1, MaskType mask) { \
GenInstrV(funct6, OP_FVF, vd, fs1, vs2, mask); \
}

Definition at line 178 of file extension-riscv-v.cc.

◆ DEFINE_OPFWV

#define DEFINE_OPFWV ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_wv(VRegister vd, VRegister vs2, VRegister vs1, \
MaskType mask) { \
GenInstrV(funct6, OP_FVV, vd, vs1, vs2, mask); \
}

Definition at line 133 of file extension-riscv-v.cc.

◆ DEFINE_OPIVI

#define DEFINE_OPIVI ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vi(VRegister vd, VRegister vs2, int8_t imm5, \
MaskType mask) { \
GenInstrV(funct6, vd, imm5, vs2, mask); \
}

Definition at line 151 of file extension-riscv-v.cc.

◆ DEFINE_OPIVV

#define DEFINE_OPIVV ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vv(VRegister vd, VRegister vs2, VRegister vs1, \
MaskType mask) { \
GenInstrV(funct6, OP_IVV, vd, vs1, vs2, mask); \
}

Definition at line 121 of file extension-riscv-v.cc.

◆ DEFINE_OPIVX

#define DEFINE_OPIVX ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vx(VRegister vd, VRegister vs2, Register rs1, \
MaskType mask) { \
GenInstrV(funct6, OP_IVX, vd, rs1, vs2, mask); \
}

Definition at line 145 of file extension-riscv-v.cc.

◆ DEFINE_OPMVV

#define DEFINE_OPMVV ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vv(VRegister vd, VRegister vs2, VRegister vs1, \
MaskType mask) { \
GenInstrV(funct6, OP_MVV, vd, vs1, vs2, mask); \
}

Definition at line 157 of file extension-riscv-v.cc.

◆ DEFINE_OPMVV_VIE

#define DEFINE_OPMVV_VIE ( name,
vs1 )
Value:
void AssemblerRISCVV::name(VRegister vd, VRegister vs2, MaskType mask) { \
GenInstrV(VXUNARY0_FUNCT6, OP_MVV, vd, vs1, vs2, mask); \
}

Definition at line 197 of file extension-riscv-v.cc.

◆ DEFINE_OPMVX

#define DEFINE_OPMVX ( name,
funct6 )
Value:
void AssemblerRISCVV::name##_vx(VRegister vd, VRegister vs2, Register rs1, \
MaskType mask) { \
GenInstrV(funct6, OP_MVX, vd, rs1, vs2, mask); \
}

Definition at line 166 of file extension-riscv-v.cc.